EPM3512AQC208-10S vs EPM3512AQC208-10NS Comparison

Detailed side-by-side comparison of EPM3512AQC208-10S by Altera and EPM3512AQC208-10NS by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3512AQC208-10S EPM3512AQC208-10NS
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Active
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macrocells 512 —
Usable Gates 1750 10,000
Logic Array Blocks (LABs) 32 (16 macrocells each) 12
Package 208-pin FineLine BGA-256 208-pin PQFP
User I/Os 208 172
Speed Grade -10 (tPD1 = 7.5 ns) —
Propagation Delay (tPD1) 7.5 ns (pin-to-pin) —
Supply Voltage - VCCINT (internal) 3.3 V —
Supply Voltage - VCCIO (I/O) 2.5 V, 3.3 V, or 5.0 V (MultiVolt) —
Programming Technology CMOS EEPROM —
In-System Programmability (ISP) Yes (IEEE Std. 1149.1 JTAG) —
PCI Compliance Yes (PCI Local Bus Specification Rev 2.2) —
Operating Temperature 0C to +70C (commercial) 0C to +70C (commercial)
Boundary-Scan (JTAG) Yes (1149.1 compliant) —
Program/Erase Endurance 100 cycles minimum —
Logic Family CMOS CMOS, EEPROM-based
Process Technology EEPROM-based CMOS —
RoHS Status [DATA_NEEDED: rohs_status] [DATA_NEEDED: rohs status]
Macro Cells — 512
Pin-to-Pin Delay (tPD) — 10 ns (speed grade -10)
Internal Counter Frequency — 227.3 MHz max
Propagation Delay — 7.5 ns (datasheet figure)
Core Supply Voltage (VCCINT) — 3.3 V
I/O Supply Voltage (VCCIO) — 2.5 V / 3.3 V / 5.0 V (MultiVolt)
Configuration — Non-volatile EEPROM, in-system programmable (JTAG IEEE 1532)
ISP Standard — IEEE Std. 1532
Mounting Type — Surface Mount

Datasheets & Resources

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