EPM3512AQC208-10S vs EPM3512AQC208-10NS 比較
詳細な並列比較: EPM3512AQC208-10S メーカー: Altera および EPM3512AQC208-10NS メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM3512AQC208-10S | EPM3512AQC208-10NS |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | 有効 |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $9.75 | $32.40 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 512 | — |
| Usable Gates | 1750 | 10,000 |
| Logic Array Blocks (LABs) | 32 (16 macrocells each) | 12 |
| パッケージ | 208-pin FineLine BGA-256 | 208-pin PQFP |
| User I/Os | 208 | 172 |
| Speed Grade | -10 (tPD1 = 7.5 ns) | — |
| Propagation Delay (tPD1) | 7.5 ns (pin-to-pin) | — |
| Supply Voltage - VCCINT (internal) | 3.3 V | — |
| Supply Voltage - VCCIO (I/O) | 2.5 V, 3.3 V, or 5.0 V (MultiVolt) | — |
| Programming Technology | CMOS EEPROM | — |
| In-System Programmability (ISP) | Yes (IEEE Std. 1149.1 JTAG) | — |
| PCI Compliance | Yes (PCI Local Bus Specification Rev 2.2) | — |
| 動作温度 | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Boundary-Scan (JTAG) | Yes (1149.1 compliant) | — |
| Program/Erase Endurance | 100 cycles minimum | — |
| Logic Family | CMOS | CMOS, EEPROM-based |
| Process Technology | EEPROM-based CMOS | — |
| RoHS ステータス | [DATA_NEEDED: rohs_status] | [DATA_NEEDED: rohs status] |
| Macro Cells | — | 512 |
| Pin-to-Pin Delay (tPD) | — | 10 ns (speed grade -10) |
| Internal Counter Frequency | — | 227.3 MHz max |
| Propagation Delay | — | 7.5 ns (datasheet figure) |
| Core Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Supply Voltage (VCCIO) | — | 2.5 V / 3.3 V / 5.0 V (MultiVolt) |
| Configuration | — | Non-volatile EEPROM, in-system programmable (JTAG IEEE 1532) |
| ISP Standard | — | IEEE Std. 1532 |
| 実装タイプ | — | Surface Mount |