EPM3512AQC208-15N vs EPM3512AQC208-3 Comparison

Detailed side-by-side comparison of EPM3512AQC208-15N by Altera and EPM3512AQC208-3 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM3512AQC208-15N EPM3512AQC208-15N - 512-Macro CPLD MAX 3000A PQFP-208 | Altera

EPM3512AQC208-15N - 512-Macro CPLD MAX 3000A PQFP-208 | Altera

EPM3512AQC208-15N ⚠ Last Time Buy

Specification Comparison

Parameter EPM3512AQC208-15N EPM3512AQC208-3
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Last Time Buy Last Time Buy
Family MAX 3000A MAX 3000A
Device Type CPLD - Complex Programmable Logic Device CPLD (Complex Programmable Logic Device)
Macro Cells 512 —
Logic Array Blocks (LABs) 16 16 (32 macrocells each)
Maximum User I/O Pins 172 172
Typical Usable Gates 12,000 —
Number of Logic Elements 512 —
Pin-to-Pin Delay (tPD) 15 ns —
Operating Supply Voltage (VCCINT) 3.3 V —
I/O Supply Voltage (VCCIO) 2.5 V / 3.3 V (MultiVolt) —
Programmable I/O Standards LVTTL, LVCMOS, PCI (with external resistor) —
In-System Programmability Yes (IEEE Std. 1532 compliant) Yes (IEEE Std. 1532 compliant)
Configuration Memory EEPROM (non-volatile) —
JTAG Support Yes (BST/Boundary-Scan Test) —
Package PQFP-208 (QC208) PQFP-208
Mounting Type Surface Mount Surface Mount
Operating Temperature 0C to +70C (commercial) [DATA_NEEDED: industrial/commercial grade range]
RoHS Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: confirm from datasheet]
Macrocells — 512
Speed Grade — -3
Supply Voltage - Core (VCCINT) — 3.3 V
I/O Bank Supply Voltage (VCCIO) — 2.5 V / 3.3 V / 5.0 V (multiVolt)
Boundary-Scan Test — Yes (IEEE Std. 1149.1 / JTAG)
Program/Erase Cycles — 100 minimum [DATA_NEEDED: exact datasheet figure]
Non-Volatile Configuration — Yes (EEPROM-based)
MSL Level — [DATA_NEEDED: moisture sensitivity level]

Datasheets & Resources

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