EPM3512AQC208-3 vs EPM3512AQC208-15N Comparison

Detailed side-by-side comparison of EPM3512AQC208-3 by Altera and EPM3512AQC208-15N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM3512AQC208-15N EPM3512AQC208-15N - 512-Macro CPLD MAX 3000A PQFP-208 | Altera

EPM3512AQC208-15N - 512-Macro CPLD MAX 3000A PQFP-208 | Altera

EPM3512AQC208-15N ⚠ Last Time Buy

Specification Comparison

Parameter EPM3512AQC208-3 EPM3512AQC208-15N
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Last Time Buy Last Time Buy
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) CPLD - Complex Programmable Logic Device
Macrocells 512 —
Logic Array Blocks (LABs) 16 (32 macrocells each) 16
Maximum User I/O Pins 172 172
Package PQFP-208 PQFP-208 (QC208)
Speed Grade -3 —
Supply Voltage - Core (VCCINT) 3.3 V —
I/O Bank Supply Voltage (VCCIO) 2.5 V / 3.3 V / 5.0 V (multiVolt) —
In-System Programmability Yes (IEEE Std. 1532 compliant) Yes (IEEE Std. 1532 compliant)
Boundary-Scan Test Yes (IEEE Std. 1149.1 / JTAG) —
Program/Erase Cycles 100 minimum [DATA_NEEDED: exact datasheet figure] —
Non-Volatile Configuration Yes (EEPROM-based) —
Operating Temperature [DATA_NEEDED: industrial/commercial grade range] 0C to +70C (commercial)
RoHS Status [DATA_NEEDED: confirm from datasheet] [DATA_NEEDED: RoHS status]
Mounting Type Surface Mount Surface Mount
MSL Level [DATA_NEEDED: moisture sensitivity level] —
Macro Cells — 512
Typical Usable Gates — 12,000
Number of Logic Elements — 512
Pin-to-Pin Delay (tPD) — 15 ns
Operating Supply Voltage (VCCINT) — 3.3 V
I/O Supply Voltage (VCCIO) — 2.5 V / 3.3 V (MultiVolt)
Programmable I/O Standards — LVTTL, LVCMOS, PCI (with external resistor)
Configuration Memory — EEPROM (non-volatile)
JTAG Support — Yes (BST/Boundary-Scan Test)

Datasheets & Resources

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