EPM3512AQC208-3 vs EPM3512AQC208-15N 对比
详细并排对比 EPM3512AQC208-3 出自 Altera 和 EPM3512AQC208-15N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
Altera
EPM3512AQC208-3 - MAX 3000A CPLD, 512 Macrocells, 172 I/O, PQFP-208 | Altera
EPM3512AQC208-3 ⚠ 最后一次采购规格对比
| 参数 | EPM3512AQC208-3 | EPM3512AQC208-15N |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 最后采购期 | 最后采购期 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $27.80 | $20.50 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD - Complex Programmable Logic Device |
| Macrocells | 512 | — |
| Logic Array Blocks (LABs) | 16 (32 macrocells each) | 16 |
| Maximum User I/O Pins | 172 | 172 |
| 封装 | PQFP-208 | PQFP-208 (QC208) |
| Speed Grade | -3 | — |
| Supply Voltage - Core (VCCINT) | 3.3 V | — |
| I/O Bank Supply Voltage (VCCIO) | 2.5 V / 3.3 V / 5.0 V (multiVolt) | — |
| In-System Programmability | Yes (IEEE Std. 1532 compliant) | Yes (IEEE Std. 1532 compliant) |
| Boundary-Scan Test | Yes (IEEE Std. 1149.1 / JTAG) | — |
| Program/Erase Cycles | 100 minimum [DATA_NEEDED: exact datasheet figure] | — |
| Non-Volatile Configuration | Yes (EEPROM-based) | — |
| 工作温度 | [DATA_NEEDED: industrial/commercial grade range] | 0C to +70C (commercial) |
| RoHS 状态 | [DATA_NEEDED: confirm from datasheet] | [DATA_NEEDED: RoHS status] |
| 安装类型 | Surface Mount | Surface Mount |
| MSL 等级 | [DATA_NEEDED: moisture sensitivity level] | — |
| Macro Cells | — | 512 |
| Typical Usable Gates | — | 12,000 |
| Number of Logic Elements | — | 512 |
| Pin-to-Pin Delay (tPD) | — | 15 ns |
| Operating Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Supply Voltage (VCCIO) | — | 2.5 V / 3.3 V (MultiVolt) |
| Programmable I/O Standards | — | LVTTL, LVCMOS, PCI (with external resistor) |
| Configuration Memory | — | EEPROM (non-volatile) |
| JTAG Support | — | Yes (BST/Boundary-Scan Test) |