EPM3512AQC20810 vs EPM3128ATC100-10N Comparison

Detailed side-by-side comparison of EPM3512AQC20810 by Altera and EPM3128ATC100-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3512AQC20810 EPM3128ATC100-10N
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete NRND
Family MAX 3000A MAX 3000A
Logic Type CPLD (EEPROM-based, non-volatile) —
Macro Cells 512 128
User I/Os 172 —
Logic Array Blocks (LABs) 16 —
Usable Gates (equivalent) 10000 —
Package 208-pin PQFP (PQ208) 100-pin TQFP (14 x 14 x 1.0 mm)
Speed Grade -10 (tPD = 10 ns) —
Propagation Delay (tPD) 10 ns 10 ns
Maximum Internal Frequency 132 MHz —
Core Supply Voltage (VCCINT) 3.3 V —
I/O Supply Voltage (VCCIO) 3.3 V —
In-System Programmability Yes (IEEE 1149.1 JTAG, 3.3 V ISP) —
PCI Compliance PCI Local Bus Specification Revision 2.2 compliant —
Operating Temperature (commercial) 0 °C to +70 °C —
Process Technology 0.30 µm CMOS EEPROM —
Configuration Memory On-chip EEPROM, non-volatile, 100+ cycles, 10+ year retention CMOS EEPROM (non-volatile, instant-on)
RoHS Status [DATA_NEEDED: RoHS status] Compliant
Product Type — CPLD (Complex Programmable Logic Device)
Usable Gates — 2500
Number of I/O — 80
Logic Elements / Blocks — 8 LABs (16 macrocells each)
Maximum Internal Frequency (fMAX) — 98 MHz
Supply Voltage VCCINT — 3.3 V
I/O Bank Voltage VCCIO — 3.3 V or 2.5 V (selectable)
In-System Programming — IEEE Std. 1532-compliant ISP via JTAG
Operating Temperature — 0 °C to +70 °C (commercial)
Mounting Type — Surface Mount
Lead-Free — Yes
MSL Level — 3 (per JEDEC J-STD-020)

Datasheets & Resources

Browse All Products Create BOM Request Quote