EPM3512AQC20810 vs EPM3128ATC100-10N 비교
다음의 상세 나란히 비교: EPM3512AQC20810 제조: Altera 및 EPM3128ATC100-10N 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
Altera
EPM3128ATC100-10N - 128-Macrocell MAX 3000A CPLD, 10ns, TQFP-100 | Intel
EPM3128ATC100-10N Nrnd사양 비교
| 파라미터 | EPM3512AQC20810 | EPM3128ATC100-10N |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | NRND |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $16.80 | $5.20 |
| Family | MAX 3000A | MAX 3000A |
| Logic Type | CPLD (EEPROM-based, non-volatile) | — |
| Macro Cells | 512 | 128 |
| User I/Os | 172 | — |
| Logic Array Blocks (LABs) | 16 | — |
| Usable Gates (equivalent) | 10000 | — |
| 패키지 | 208-pin PQFP (PQ208) | 100-pin TQFP (14 x 14 x 1.0 mm) |
| Speed Grade | -10 (tPD = 10 ns) | — |
| Propagation Delay (tPD) | 10 ns | 10 ns |
| Maximum Internal Frequency | 132 MHz | — |
| Core Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 3.3 V | — |
| In-System Programmability | Yes (IEEE 1149.1 JTAG, 3.3 V ISP) | — |
| PCI Compliance | PCI Local Bus Specification Revision 2.2 compliant | — |
| Operating Temperature (commercial) | 0 °C to +70 °C | — |
| Process Technology | 0.30 µm CMOS EEPROM | — |
| Configuration Memory | On-chip EEPROM, non-volatile, 100+ cycles, 10+ year retention | CMOS EEPROM (non-volatile, instant-on) |
| RoHS 상태 | [DATA_NEEDED: RoHS status] | Compliant |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Usable Gates | — | 2500 |
| Number of I/O | — | 80 |
| Logic Elements / Blocks | — | 8 LABs (16 macrocells each) |
| Maximum Internal Frequency (fMAX) | — | 98 MHz |
| Supply Voltage VCCINT | — | 3.3 V |
| I/O Bank Voltage VCCIO | — | 3.3 V or 2.5 V (selectable) |
| In-System Programming | — | IEEE Std. 1532-compliant ISP via JTAG |
| 동작 온도 | — | 0 °C to +70 °C (commercial) |
| 실장 유형 | — | Surface Mount |
| Lead-Free | — | Yes |
| MSL 레벨 | — | 3 (per JEDEC J-STD-020) |