EPM3512AQC210-7 vs EPM3512AQC208-7 Comparison

Detailed side-by-side comparison of EPM3512AQC210-7 by Altera and EPM3512AQC208-7 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3512AQC210-7 EPM3512AQC208-7
Brand Altera Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Nrnd Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $21.85 $41.72
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macrocells 512 512
Logic Array Blocks (LABs) 16 β€”
Maximum User I/O Pins 172 β€”
Dedicated Input Pins 12 β€”
Package PQFP-208 208-Pin PQFP (FQFP, gull-wing)
Pin Count 208 β€”
Mounting Type Surface Mount β€”
Operating Voltage (Core) 3.3 V β€”
Min Supply Voltage 3.0 V β€”
Max Supply Voltage 3.6 V β€”
I/O Voltage Support 1.8 V / 2.5 V / 3.3 V / 5.0 V (MultiVolt I/O) β€”
Pin-to-Pin Delay 7 ns (speed grade -7) β€”
Speed Grade 7 ns β€”
In-System Programmability Yes (JTAG, IEEE 1149.1) β€”
Operating Temperature [DATA_NEEDED: operating temperature range] 0 C to +70 C (commercial)
Non-Volatile Configuration Yes (EEPROM-based) β€”
RoHS Status [DATA_NEEDED: RoHS compliance] Compliant
Usable Gates β€” 10,000
Propagation Delay (tPD) β€” 7.5 ns
Counter Frequency (fCNT) β€” 116.3 MHz
User I/Os β€” 172
Logic Elements / LEs β€” N/A (CPLD macrocell architecture)
Supply Voltage (VCCINT) β€” 3.3 V
I/O Standards Supported β€” 5.0 V, 3.3 V, 2.5 V (MultiVolt I/O)
Programming β€” In-System Programmable via JTAG (IEEE Std. 1532)
Process Technology β€” CMOS EEPROM, 0.30 um
Lead-Free β€” Yes

Datasheets & Resources

Browse All Products Create BOM Request Quote