EPM3512AQI208-10N vs EPM3512AQ208-10N Comparison
Detailed side-by-side comparison of EPM3512AQI208-10N by Intel and EPM3512AQ208-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM3512AQ208-10N - MAX 3000A CPLD, 512 Macrocells, 172 I/O | Altera
EPM3512AQ208-10N β ActiveSpecification Comparison
| Parameter | EPM3512AQI208-10N | EPM3512AQ208-10N |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $12.90 | $21.40 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Logic Family | CMOS EEPROM-based | β |
| Macro Cells | 512 | β |
| Logic Array Blocks (LABs) | 12 | 32 |
| User I/Os | 172 (max), 208-pin package | 172 |
| Propagation Delay (tPD) | 10 ns | β |
| Supply Voltage | 3.3 V | β |
| I/O Standards | MultiVolt (2.5 V / 3.3 V / 5 V tolerant) | β |
| Package Type | PQFP-208 (FINE LINE BGA-style 256-pin land) | β |
| Pins | 256 (package), 208 used | β |
| Operating Temperature | 0C to 70C | β |
| Mounting Type | Surface Mount | Surface Mount |
| Programming Interface | JTAG (IEEE 1149.1) / ISP (IEEE 1532) | IEEE Std. 1532 (JTAG) ISP |
| Compliance | RoHS status unknown from data | β |
| Boundary Scan | Built-in BST (IEEE 1149.1) | β |
| Configuration Memory | On-chip EEPROM, non-volatile | β |
| Macrocells | β | 512 |
| Usable Gates | β | 10,000 |
| Package | β | 208-pin PQFP |
| Speed Grade | β | -10 (10 ns pin-to-pin delay) |
| Pin-to-Pin Delay (tPD) | β | 4.5 ns (typical) |
| Maximum Frequency (fCNT) | β | 227.3 MHz |
| Core Supply Voltage (VCCINT) | β | 3.3 V |
| I/O Supply Voltage (VCCIO) | β | 2.5 V, 3.3 V, or 5.0 V |
| Process Technology | β | CMOS EEPROM |
| Operating Temperature (Industrial) | β | -40 C to +85 C |
| RoHS Status | β | unknown |