EPM3512AQI208-10N vs EPM3512AQ208-10N Vergleich
Detaillierter Direktvergleich von EPM3512AQI208-10N von Intel und EPM3512AQ208-10N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM3512AQI208-10N | EPM3512AQ208-10N |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $12,90 | $21,40 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Logic Family | CMOS EEPROM-based | — |
| Macro Cells | 512 | — |
| Logic Array Blocks (LABs) | 12 | 32 |
| User I/Os | 172 (max), 208-pin package | 172 |
| Propagation Delay (tPD) | 10 ns | — |
| Versorgungsspannung | 3.3 V | — |
| I/O Standards | MultiVolt (2.5 V / 3.3 V / 5 V tolerant) | — |
| Package Type | PQFP-208 (FINE LINE BGA-style 256-pin land) | — |
| Pins | 256 (package), 208 used | — |
| Betriebstemperatur | 0C to 70C | — |
| Montageart | Surface Mount | Surface Mount |
| Programming Interface | JTAG (IEEE 1149.1) / ISP (IEEE 1532) | IEEE Std. 1532 (JTAG) ISP |
| Compliance | RoHS status unknown from data | — |
| Boundary Scan | Built-in BST (IEEE 1149.1) | — |
| Configuration Memory | On-chip EEPROM, non-volatile | — |
| Macrocells | — | 512 |
| Usable Gates | — | 10,000 |
| Gehäuse | — | 208-pin PQFP |
| Speed Grade | — | -10 (10 ns pin-to-pin delay) |
| Pin-to-Pin Delay (tPD) | — | 4.5 ns (typical) |
| Maximum Frequency (fCNT) | — | 227.3 MHz |
| Core Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Supply Voltage (VCCIO) | — | 2.5 V, 3.3 V, or 5.0 V |
| Process Technology | — | CMOS EEPROM |
| Operating Temperature (Industrial) | — | -40 C to +85 C |
| RoHS-Status | — | unknown |