EPM3512AQI208-7N vs EPM3512AQC208-7N Comparison
Detailed side-by-side comparison of EPM3512AQI208-7N by Intel and EPM3512AQC208-7N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM3512AQC208-7N - 512-Macro MAX 3000A CPLD, 208-PQFP | Altera
EPM3512AQC208-7N β Last Time BuySpecification Comparison
| Parameter | EPM3512AQI208-7N | EPM3512AQC208-7N |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $18.45 | $41.41 |
| Family | MAX 3000A | MAX 3000A |
| Product Type | CPLD (Complex Programmable Logic Device) | β |
| Usable Gates | 10,000 | β |
| Macrocells | 512 | β |
| Logic Array Blocks (LABs) | 16 | 32 |
| Maximum Operating Frequency | 116.3 MHz | β |
| Core Supply Voltage (VCCINT) | 3.3 V | β |
| I/O Supply Voltage (VCCIO) | 2.5 V / 3.3 V / 5.0 V (MultiVolt) | β |
| Package | 208-pin PQFP | 208-Pin PQFP / FQFP-208 (Plastic Quad Flat Pack, gull-wing) |
| Programming Interface | IEEE 1149.1 JTAG (in-system programmable) | β |
| Configuration Memory | EEPROM (non-volatile) | β |
| Speed Grade | 7 (7N suffix) | -7 |
| Operating Temperature | Industrial (per 'N' suffix) | 0 Β°C to +70 Β°C (commercial) |
| Pin Count | 208 | β |
| Mounting Type | Surface Mount | β |
| RoHS Status | Compliant | Compliant |
| User I/O Pins | [DATA_NEEDED: exact user I/O count for PQFP-208] | β |
| Propagation Delay (tPD) | [DATA_NEEDED: tPD in ns per speed grade 7] | 7.5 ns |
| Logic Capacity | β | 512 macrocells, 10,000 usable gates |
| Macrocells per LAB | β | 16 |
| User I/Os | β | 172 |
| Maximum Frequency (fCNT) | β | 116.3 MHz |
| Supply Voltage (VCCINT) | β | 3.3 V (3.0 V to 3.6 V) |
| I/O Bank Count | β | 4 (MultiVolt) |
| Supported I/O Standards | β | 1.8 V / 2.5 V / 3.3 V LVTTL/LVCMOS |
| Process Technology | β | 0.30 Β΅m CMOS EEPROM |
| Configuration | β | Non-volatile EEPROM, in-system programmable (ISP) |
| JTAG Interface | β | IEEE 1149.1 BST + IEEE 1532 ISP |