EPM3512AQI208-7N vs EPM3512AQC208-7N Vergleich
Detaillierter Direktvergleich von EPM3512AQI208-7N von Intel und EPM3512AQC208-7N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM3512AQC208-7N - 512-Macro MAX 3000A CPLD, 208-PQFP | Altera
EPM3512AQC208-7N ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EPM3512AQI208-7N | EPM3512AQC208-7N |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Letzte Kaufgelegenheit |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $18,45 | $41,41 |
| Family | MAX 3000A | MAX 3000A |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Usable Gates | 10,000 | — |
| Macrocells | 512 | — |
| Logic Array Blocks (LABs) | 16 | 32 |
| Maximum Operating Frequency | 116.3 MHz | — |
| Core Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 2.5 V / 3.3 V / 5.0 V (MultiVolt) | — |
| Gehäuse | 208-pin PQFP | 208-Pin PQFP / FQFP-208 (Plastic Quad Flat Pack, gull-wing) |
| Programming Interface | IEEE 1149.1 JTAG (in-system programmable) | — |
| Configuration Memory | EEPROM (non-volatile) | — |
| Speed Grade | 7 (7N suffix) | -7 |
| Betriebstemperatur | Industrial (per 'N' suffix) | 0 °C to +70 °C (commercial) |
| Pin-Anzahl | 208 | — |
| Montageart | Surface Mount | — |
| RoHS-Status | Compliant | Compliant |
| User I/O Pins | [DATA_NEEDED: exact user I/O count for PQFP-208] | — |
| Propagation Delay (tPD) | [DATA_NEEDED: tPD in ns per speed grade 7] | 7.5 ns |
| Logic Capacity | — | 512 macrocells, 10,000 usable gates |
| Macrocells per LAB | — | 16 |
| User I/Os | — | 172 |
| Maximum Frequency (fCNT) | — | 116.3 MHz |
| Supply Voltage (VCCINT) | — | 3.3 V (3.0 V to 3.6 V) |
| I/O Bank Count | — | 4 (MultiVolt) |
| Supported I/O Standards | — | 1.8 V / 2.5 V / 3.3 V LVTTL/LVCMOS |
| Process Technology | — | 0.30 µm CMOS EEPROM |
| Configuration | — | Non-volatile EEPROM, in-system programmable (ISP) |
| JTAG Interface | — | IEEE 1149.1 BST + IEEE 1532 ISP |