EPM5016DC-17 vs EPM5016DI-20 Comparison
Detailed side-by-side comparison of EPM5016DC-17 by Altera and EPM5016DI-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5016DC-17 | EPM5016DI-20 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 |
| Macrocells | 16 | 16 |
| Logic Elements | [DATA_NEEDED: LE count for MAX 5000 family] | — |
| User I/O Pins (max) | 24 | — |
| Propagation Delay (tPD) | 17 ns | 20 ns |
| Counter Frequency (fCNT) | 67 MHz | — |
| Supply Voltage (VCC) | 5 V | — |
| I/O Standard | TTL-compatible | — |
| Process Technology | 0.75 micron CMOS EEPROM | — |
| Package | Ceramic DIP-24 (DC suffix) | 20-pin Ceramic DIP (DI), windowed |
| Pin Count | 24 | — |
| Mounting Type | Through-hole | — |
| Operating Temperature | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature range] |
| In-System Programmability | Yes (ByteBlaster / BitBlaster) | — |
| Configuration Memory | On-chip EEPROM (non-volatile) | — |
| RoHS Status | [DATA_NEEDED: confirmed compliance status from manufacturer] | [DATA_NEEDED: RoHS compliance] |
| Device Type | — | EPLD (UV-erasable CMOS) |
| Maximum Clock Frequency | — | 62.5 MHz |
| Total Inputs | — | 16 |
| Dedicated Inputs | — | 7 |
| Configurable I/O Pins | — | 8 |
| External Clock Inputs | — | 1 |
| Product Terms per Output | — | 8 |
| Output Functions per Macrocell | — | 8 |
| Technology | — | CMOS EPROM |
| Programmable Interconnect | — | PIA (Programmable Interconnect Array) |
| Speed Grade | — | -20 (20 ns tPD) |
| Supply Voltage | — | [DATA_NEEDED: VCC nominal] |