EPM5016DC-20 vs EPM5016LC-17 Comparison
Detailed side-by-side comparison of EPM5016DC-20 by Altera and EPM5016LC-17 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5016DC-20 | EPM5016LC-17 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 EPLD |
| Device Type | EPLD (UV-Erasable Programmable Logic Device) | — |
| Macrocells | 16 | 16 |
| Product Terms | 160 | 160 |
| Dedicated Inputs | 7 | 7 |
| I/O Pins | 8 | 8 |
| Propagation Delay (tPD) | 20 ns | 17 ns |
| Maximum Clock Frequency | 62.5 MHz | — |
| Maximum Supply Voltage | 5.25 V | — |
| Nominal Supply Voltage | 5.0 V | — |
| Process Technology | CMOS, UV-erasable | — |
| Architecture | PAL-type macrocell with Programmable Interconnect Array (PIA) | PAL-type with Programmable Interconnect Array (PIA) |
| Package Type | 20-pin Ceramic DIP (Cerdip) with UV window | — |
| Package Suffix Code | DC = Ceramic DIP, Commercial | — |
| Speed Grade | -20 = 20 ns tPD | — |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: temperature grade] |
| Programming Method | UV erase + EPROM-style programming via Altera programming hardware | — |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS compliance] |
| Technology | — | CMOS, UV-erasable |
| Total Input Pins | — | 16 |
| Outputs | — | 8 |
| External Clock Inputs | — | 1 |
| Package | — | Windowed Ceramic DIP (LC) |
| Supply Voltage | — | [DATA_NEEDED: VCC range] |
| Logic Compatibility | — | TTL/CMOS |