EPM5016DC-20 vs EPM5016LC-17 Vergleich
Detaillierter Direktvergleich von EPM5016DC-20 von Altera und EPM5016LC-17 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM5016DC-20 | EPM5016LC-17 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $16,50 | $10,95 |
| Family | MAX 5000 | MAX 5000 EPLD |
| Device Type | EPLD (UV-Erasable Programmable Logic Device) | — |
| Macrocells | 16 | 16 |
| Product Terms | 160 | 160 |
| Dedicated Inputs | 7 | 7 |
| I/O Pins | 8 | 8 |
| Propagation Delay (tPD) | 20 ns | 17 ns |
| Maximale Taktfrequenz | 62.5 MHz | — |
| Maximum Supply Voltage | 5.25 V | — |
| Nominal Supply Voltage | 5.0 V | — |
| Process Technology | CMOS, UV-erasable | — |
| Architecture | PAL-type macrocell with Programmable Interconnect Array (PIA) | PAL-type with Programmable Interconnect Array (PIA) |
| Package Type | 20-pin Ceramic DIP (Cerdip) with UV window | — |
| Package Suffix Code | DC = Ceramic DIP, Commercial | — |
| Speed Grade | -20 = 20 ns tPD | — |
| Betriebstemperatur | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: temperature grade] |
| Programming Method | UV erase + EPROM-style programming via Altera programming hardware | — |
| RoHS-Status | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS compliance] |
| Technology | — | CMOS, UV-erasable |
| Total Input Pins | — | 16 |
| Outputs | — | 8 |
| External Clock Inputs | — | 1 |
| Gehäuse | — | Windowed Ceramic DIP (LC) |
| Versorgungsspannung | — | [DATA_NEEDED: VCC range] |
| Logic Compatibility | — | TTL/CMOS |