EPM5016DC-20 vs EPM5032DC20 Comparison
Detailed side-by-side comparison of EPM5016DC-20 by Altera and EPM5032DC20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5016DC-20 | EPM5032DC20 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | MAX 5000 | — |
| Device Type | EPLD (UV-Erasable Programmable Logic Device) | — |
| Macrocells | 16 | 32 |
| Product Terms | 160 | — |
| Dedicated Inputs | 7 | 7 |
| I/O Pins | 8 | 16 (bidirectional) |
| Propagation Delay (tPD) | 20 ns | 20 ns |
| Maximum Clock Frequency | 62.5 MHz | — |
| Maximum Supply Voltage | 5.25 V | — |
| Nominal Supply Voltage | 5.0 V | — |
| Process Technology | CMOS, UV-erasable | CMOS |
| Architecture | PAL-type macrocell with Programmable Interconnect Array (PIA) | PAL-type with Programmable Interconnect Array (PIA) |
| Package Type | 20-pin Ceramic DIP (Cerdip) with UV window | — |
| Package Suffix Code | DC = Ceramic DIP, Commercial | — |
| Speed Grade | -20 = 20 ns tPD | — |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| Programming Method | UV erase + EPROM-style programming via Altera programming hardware | — |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS compliance] |
| Device Family | — | MAX 5000 |
| Product Type | — | UV-erasable PLD (CPLD class) |
| Usable Gates | — | 600 |
| Maximum Frequency (Fmax) | — | 71.4 MHz |
| Supply Voltage (VCC) | — | 5 V (4.75 V to 5.25 V) |
| Total Inputs (max) | — | 24 |
| Output Macrocells | — | 16 |
| Clock Inputs | — | 1 (global) |
| Package | — | 20-pin Ceramic DIP (DC) with UV window |
| Mounting Type | — | Through-Hole (DIP) |