EPM5016DC-20 vs EPM5032DC20 对比
详细并排对比 EPM5016DC-20 出自 Altera 和 EPM5032DC20 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPM5016DC-20 | EPM5032DC20 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $16.50 | $8.20 |
| Family | MAX 5000 | — |
| Device Type | EPLD (UV-Erasable Programmable Logic Device) | — |
| Macrocells | 16 | 32 |
| Product Terms | 160 | — |
| Dedicated Inputs | 7 | 7 |
| I/O Pins | 8 | 16 (bidirectional) |
| Propagation Delay (tPD) | 20 ns | 20 ns |
| 最大时钟频率 | 62.5 MHz | — |
| Maximum Supply Voltage | 5.25 V | — |
| Nominal Supply Voltage | 5.0 V | — |
| Process Technology | CMOS, UV-erasable | CMOS |
| Architecture | PAL-type macrocell with Programmable Interconnect Array (PIA) | PAL-type with Programmable Interconnect Array (PIA) |
| Package Type | 20-pin Ceramic DIP (Cerdip) with UV window | — |
| Package Suffix Code | DC = Ceramic DIP, Commercial | — |
| Speed Grade | -20 = 20 ns tPD | — |
| 工作温度 | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| Programming Method | UV erase + EPROM-style programming via Altera programming hardware | — |
| RoHS 状态 | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS compliance] |
| Device Family | — | MAX 5000 |
| Product Type | — | UV-erasable PLD (CPLD class) |
| Usable Gates | — | 600 |
| Maximum Frequency (Fmax) | — | 71.4 MHz |
| Supply Voltage (VCC) | — | 5 V (4.75 V to 5.25 V) |
| Total Inputs (max) | — | 24 |
| Output Macrocells | — | 16 |
| Clock Inputs | — | 1 (global) |
| 封装 | — | 20-pin Ceramic DIP (DC) with UV window |
| 安装类型 | — | Through-Hole (DIP) |