EPM5016DI-20 vs EPM5016DC-15 Comparison
Detailed side-by-side comparison of EPM5016DI-20 by Altera and EPM5016DC-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5016DI-20 | EPM5016DC-15 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | MAX 5000 | — |
| Device Type | EPLD (UV-erasable CMOS) | — |
| Macrocells | 16 | 16 |
| Propagation Delay (tPD) | 20 ns | — |
| Maximum Clock Frequency | 62.5 MHz | — |
| Total Inputs | 16 | — |
| Dedicated Inputs | 7 | 4 |
| Configurable I/O Pins | 8 | — |
| External Clock Inputs | 1 | — |
| Product Terms per Output | 8 | — |
| Output Functions per Macrocell | 8 | — |
| Technology | CMOS EPROM | — |
| Programmable Interconnect | PIA (Programmable Interconnect Array) | — |
| Package | 20-pin Ceramic DIP (DI), windowed | Ceramic DIP-24 (windowed) |
| Speed Grade | -20 (20 ns tPD) | — |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | 0 °C to 70 °C (commercial) |
| Supply Voltage | [DATA_NEEDED: VCC nominal] | — |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS status - pre-RoHS era part, likely non-compliant] |
| Device Family | — | MAX 5000 |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Logic Array Blocks (LABs) | — | 2 |
| User I/O Pins | — | 12 |
| Pin-to-Pin Delay (tpd) | — | 15 ns |
| Maximum Frequency (fmax) | — | 71 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Programming Voltage (VPP) | — | 12.75 V |
| Mounting Type | — | Through-Hole |
| Process Technology | — | CMOS EPROM |
| Configuration Memory | — | Non-volatile UV-erasable EPROM |
| Lead Finish | — | [DATA_NEEDED: lead-free status] |