EPM5032JC-20 vs EPM5032LC-15 Comparison
Detailed side-by-side comparison of EPM5032JC-20 by Altera and EPM5032LC-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5032JC-20 | EPM5032LC-15 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Product Type | UV-erasable Programmable Logic Device (PLD) | — |
| Family | MAX 5000 | MAX 5000 EPLD |
| Macrocells | 32 | 32 |
| Logic Array Blocks (LABs) | 1 | 4 |
| Product Terms (P-terms) | 320 | — |
| Propagation Delay (tPD) | 20 ns | — |
| Maximum Clock Frequency | 62.5 MHz | — |
| Setup Time | 10 ns | — |
| I/O Lines | 16 (bidirectional) | — |
| Dedicated Inputs | 8 | 7 |
| Total Inputs | 24 | — |
| Package | 68-pin JLCC (windowed ceramic) | JLCC-28 (windowed ceramic) |
| Process Technology | CMOS | — |
| Erase Method | UV (12V VPP + ultraviolet exposure) | — |
| Programming Voltage (VPP) | 12 V | — |
| Architecture | PAL-type AND-OR array with PIA interconnect | PAL-type AND/OR with PIA |
| Lifecycle Status | Obsolete (legacy Altera MAX 5000) | — |
| Usable Gates | — | 600 |
| Bidirectional I/O Pins | — | 16 |
| Maximum Operating Frequency | — | 83.3 MHz |
| Pin-to-Pin Delay (tPD) | — | 15 ns |
| Supply Voltage (VCC) | — | 5 V (4.75 V to 5.25 V) |
| Technology | — | CMOS EPROM, 1.0 um process |
| Programmability | — | UV-Erasable / OTP |
| Operating Temperature | — | 0C to +70C (commercial) |
| RoHS Status | — | Non-compliant (contains Pb, ceramic-windowed package) |