EPM5032JC vs EPM5032LC-25 Comparison
Detailed side-by-side comparison of EPM5032JC by Altera and EPM5032LC-25 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5032JC | EPM5032LC-25 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $13.50 | $8.20 |
| Family | MAX 5000 EPLD | β |
| Macrocells | 32 | 32 |
| Logic Gates | 600 usable gates | β |
| Maximum I/O Pins | 40 | β |
| Propagation Delay (tPD) | [DATA_NEEDED: specific speed grade value] | 25 ns |
| Supply Voltage (VCC) | 5 V | 5 V Β±10% (4.5 V to 5.5 V) |
| Input Type | TTL-compatible | β |
| Output Type | TTL/CMOS-compatible | β |
| Package | PLCC-44 | 28-pin PLCC (JEDEC S-PQCC-J28), 1.27 mm pitch |
| Operating Temperature | 0C to +70C (commercial) | 0 Β°C to +70 Β°C (commercial, "LC" suffix) |
| Mounting Type | Surface Mount (J-lead) | Surface Mount, socket-compatible |
| Programmability | UV-erasable (windowed ceramic) / OTP variants | β |
| Design Software | MAX+PLUS II / Quartus legacy | β |
| JEDEC Standard | JEDEC PLCC-44 footprint | β |
| RoHS Status | unknown | Not RoHS compliant (legacy Altera product) |
| Lead-Free | unknown | β |
| Device Family | β | MAX 5000 |
| Architecture | β | PAL-type EPLD (Erasable Programmable Logic Device) |
| Technology | β | CMOS, UV-erasable / OTP |
| Product Terms | β | 320 |
| Dedicated Inputs | β | 7 |
| I/O Pins | β | 16 bidirectional |
| Total Inputs | β | 24 (7 dedicated + 16 I/O used as input) |
| Maximum Internal Frequency | β | 62.5 MHz |
| I/O Standard | β | 5 V CMOS |
| Configuration Cell | β | Programmable interconnect array (PIA), OTP / UV-erasable |