EPM5032JC vs EPM5032LC-25 Comparación
Comparación detallada lado a lado de EPM5032JC por Altera y EPM5032LC-25 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM5032JC | EPM5032LC-25 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $13,50 | $8,20 |
| Family | MAX 5000 EPLD | — |
| Macrocells | 32 | 32 |
| Logic Gates | 600 usable gates | — |
| Maximum I/O Pins | 40 | — |
| Propagation Delay (tPD) | [DATA_NEEDED: specific speed grade value] | 25 ns |
| Supply Voltage (VCC) | 5 V | 5 V ±10% (4.5 V to 5.5 V) |
| Input Type | TTL-compatible | — |
| Tipo de salida | TTL/CMOS-compatible | — |
| Encapsulado | PLCC-44 | 28-pin PLCC (JEDEC S-PQCC-J28), 1.27 mm pitch |
| Temperatura de funcionamiento | 0C to +70C (commercial) | 0 °C to +70 °C (commercial, "LC" suffix) |
| Tipo de montaje | Surface Mount (J-lead) | Surface Mount, socket-compatible |
| Programmability | UV-erasable (windowed ceramic) / OTP variants | — |
| Design Software | MAX+PLUS II / Quartus legacy | — |
| JEDEC Standard | JEDEC PLCC-44 footprint | — |
| Estado RoHS | unknown | Not RoHS compliant (legacy Altera product) |
| Lead-Free | unknown | — |
| Device Family | — | MAX 5000 |
| Architecture | — | PAL-type EPLD (Erasable Programmable Logic Device) |
| Technology | — | CMOS, UV-erasable / OTP |
| Product Terms | — | 320 |
| Dedicated Inputs | — | 7 |
| I/O Pins | — | 16 bidirectional |
| Total Inputs | — | 24 (7 dedicated + 16 I/O used as input) |
| Maximum Internal Frequency | — | 62.5 MHz |
| I/O Standard | — | 5 V CMOS |
| Configuration Cell | — | Programmable interconnect array (PIA), OTP / UV-erasable |