EPM5032JC25 vs EPM5032JC-20 Comparison
Detailed side-by-side comparison of EPM5032JC25 by Altera and EPM5032JC-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5032JC25 | EPM5032JC-20 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 |
| Device | EPM5032 | — |
| Logic Elements | 32 macrocells | — |
| Propagation Delay (tPD) | 25 ns | 20 ns |
| Maximum Internal Frequency | 62.5 MHz | — |
| Product Terms | 320 | — |
| Flip-Flops | 32 | — |
| Dedicated Inputs | 7 | 8 |
| Bidirectional I/O Pins | 16 | — |
| Total Inputs to Array | 24 | — |
| Number of Outputs | 16 | — |
| Architecture | PAL-type macrocells with global Programmable Interconnect Array (PIA) | PAL-type AND-OR array with PIA interconnect |
| Technology | CMOS EPROM, UV-erasable (windowed) / OTP | — |
| Supply Voltage | 5 V (TTL-level I/O) | — |
| Package | 28-pin PLCC (JC) | 68-pin JLCC (windowed ceramic) |
| Mounting Type | Surface Mount | — |
| RoHS Status | [DATA_NEEDED: RoHS status] | — |
| Product Type | — | UV-erasable Programmable Logic Device (PLD) |
| Macrocells | — | 32 |
| Logic Array Blocks (LABs) | — | 1 |
| Product Terms (P-terms) | — | 320 |
| Maximum Clock Frequency | — | 62.5 MHz |
| Setup Time | — | 10 ns |
| I/O Lines | — | 16 (bidirectional) |
| Total Inputs | — | 24 |
| Process Technology | — | CMOS |
| Erase Method | — | UV (12V VPP + ultraviolet exposure) |
| Programming Voltage (VPP) | — | 12 V |
| Lifecycle Status | — | Obsolete (legacy Altera MAX 5000) |