EPM5032JC25 vs EPM5032JC-20 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5032JC25 sa pamamagitan ng Altera at EPM5032JC-20 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5032JC25 | EPM5032JC-20 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 |
| Device | EPM5032 | — |
| Logic Elements | 32 macrocells | — |
| Propagation Delay (tPD) | 25 ns | 20 ns |
| Maximum Internal Frequency | 62.5 MHz | — |
| Product Terms | 320 | — |
| Flip-Flops | 32 | — |
| Dedicated Inputs | 7 | 8 |
| Bidirectional I/O Pins | 16 | — |
| Total Inputs to Array | 24 | — |
| Bilang ng Outputs | 16 | — |
| Architecture | PAL-type macrocells with global Programmable Interconnect Array (PIA) | PAL-type AND-OR array with PIA interconnect |
| Technology | CMOS EPROM, UV-erasable (windowed) / OTP | — |
| Volte ng Pagbibigay | 5 V (TTL-level I/O) | — |
| Packhaging | 28-pin PLCC (JC) | 68-pin JLCC (windowed ceramic) |
| Uri ng Pagpapasok | Surface Mount | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | — |
| Product Type | — | UV-erasable Programmable Logic Device (PLD) |
| Macrocells | — | 32 |
| Logic Array Blocks (LABs) | — | 1 |
| Product Terms (P-terms) | — | 320 |
| Maksimum na Taktiko ng Oras | — | 62.5 MHz |
| Setup Time | — | 10 ns |
| I/O Lines | — | 16 (bidirectional) |
| Total Inputs | — | 24 |
| Process Technology | — | CMOS |
| Erase Method | — | UV (12V VPP + ultraviolet exposure) |
| Programming Voltage (VPP) | — | 12 V |
| Katayuan ng Lifecycle | — | Obsolete (legacy Altera MAX 5000) |