EPM5064LC-1 vs EPM5064JC-1 Comparison

Detailed side-by-side comparison of EPM5064LC-1 by Altera and EPM5064JC-1 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM5064LC-1 EPM5064JC-1
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $9.95 $18.25
Product Type CPLD (Complex Programmable Logic Device) β€”
Family MAX 5000 MAX 5000
Macrocells 64 β€”
Logic Array Blocks (LABs) 4 β€”
Usable Gates 1.25K (approx.) 1250 (typical)
Supply Voltage (VCC) 4.75 V to 5.25 V 5 V nominal (4.75 V – 5.25 V)
Internal Operating Frequency 62.5 MHz β€”
Propagation Delay (tPD) 40 ns β€”
Input Lines 36 β€”
Dedicated Inputs 7 [DATA_NEEDED: dedicated input count]
Output Lines 28 β€”
Programming Technology OTP / UV-Erasable EPROM β€”
Package 44-pin PLCC (Plastic Leaded Chip Carrier) 44-pin PLCC (J-lead, windowed ceramic)
Process Technology CMOS 0.8 Β΅m CMOS
Operating Temperature [DATA_NEEDED: operating temperature range] 0 Β°C to +70 Β°C (commercial, -JC suffix)
RoHS Status [DATA_NEEDED: RoHS compliance] Non-compliant (windowed ceramic, contains Pb in glass frit)
Programming Interface JTAG (ByteBlaster-compatible) β€”
Device Type β€” EPLD (Erasable Programmable Logic Device)
Macro Cells β€” 64
Logic Elements β€” 128 (Logic Array Blocks)
Maximum Operating Frequency β€” 33.3 MHz (fCNT)
Pin-to-Pin Delay (tPD) β€” [DATA_NEEDED: tPD typical/max in ns]
Programmable Pins β€” 36 (typical I/O, 44-pin PLCC)
Mounting Type β€” Surface Mount (PLCC socket recommended)
Erasure Method β€” UV-erasable through quartz window
Programming Method β€” Altera Logic Programmer + MasterBlaster/ByteBlasterMV
JTAG Boundary Scan β€” Not supported (classic MAX architecture)
Military/Avionics SMD β€” 5962-01-417-3750 (QML variant: EPM5064JM/883)

Datasheets & Resources

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