EPM5064LC-1 vs EPM5064JC-1 Comparaison
Comparaison détaillée côte à côte de EPM5064LC-1 par Altera et EPM5064JC-1 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM5064LC-1 | EPM5064JC-1 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $9,95 | $18,25 |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Family | MAX 5000 | MAX 5000 |
| Macrocells | 64 | — |
| Logic Array Blocks (LABs) | 4 | — |
| Usable Gates | 1.25K (approx.) | 1250 (typical) |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 5 V nominal (4.75 V – 5.25 V) |
| Internal Operating Frequency | 62.5 MHz | — |
| Propagation Delay (tPD) | 40 ns | — |
| Input Lines | 36 | — |
| Dedicated Inputs | 7 | [DATA_NEEDED: dedicated input count] |
| Output Lines | 28 | — |
| Programming Technology | OTP / UV-Erasable EPROM | — |
| Boîtier | 44-pin PLCC (Plastic Leaded Chip Carrier) | 44-pin PLCC (J-lead, windowed ceramic) |
| Process Technology | CMOS | 0.8 µm CMOS |
| Température de fonctionnement | [DATA_NEEDED: operating temperature range] | 0 °C to +70 °C (commercial, -JC suffix) |
| Statut RoHS | [DATA_NEEDED: RoHS compliance] | Non-compliant (windowed ceramic, contains Pb in glass frit) |
| Programming Interface | JTAG (ByteBlaster-compatible) | — |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Macro Cells | — | 64 |
| Logic Elements | — | 128 (Logic Array Blocks) |
| Maximum Operating Frequency | — | 33.3 MHz (fCNT) |
| Pin-to-Pin Delay (tPD) | — | [DATA_NEEDED: tPD typical/max in ns] |
| Programmable Pins | — | 36 (typical I/O, 44-pin PLCC) |
| Type de montage | — | Surface Mount (PLCC socket recommended) |
| Erasure Method | — | UV-erasable through quartz window |
| Programming Method | — | Altera Logic Programmer + MasterBlaster/ByteBlasterMV |
| JTAG Boundary Scan | — | Not supported (classic MAX architecture) |
| Military/Avionics SMD | — | 5962-01-417-3750 (QML variant: EPM5064JM/883) |