EPM5064LC-2 vs EPM5064LC-1 Comparison
Detailed side-by-side comparison of EPM5064LC-2 by Altera and EPM5064LC-1 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5064LC-2 | EPM5064LC-1 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Device Family | MAX 5000 | — |
| Product Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 64 | 64 |
| Logic Array Blocks (LABs) | 4 | 4 |
| Logic Elements per LAB | 16 | — |
| Number of Inputs | 36 (7 dedicated + 28 I/O) | — |
| Number of I/O Pins | 28 | — |
| Number of Flip-Flops | 28 | — |
| Propagation Delay (tPD) | 45 ns | 40 ns |
| Maximum Internal Frequency | 40 MHz | — |
| Process Technology | CMOS, OTP EPROM (UV-erasable base) | CMOS |
| Programmable Polarity | Yes | — |
| Programmable Output Enable | Yes, per macrocell | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 4.75 V to 5.25 V |
| Operating Temperature | -40 C to +85 C (commercial LC grade) [DATA_NEEDED: explicit min/max in source] | [DATA_NEEDED: operating temperature range] |
| Package | PLCC-44 (J-Lead, plastic) | 44-pin PLCC (Plastic Leaded Chip Carrier) |
| Mounting Type | Surface Mount | — |
| RoHS Status | [DATA_NEEDED: not specified in source] | [DATA_NEEDED: RoHS compliance] |
| Programming Method | Altera byte-wide / JTAG programmer | — |
| Family | — | MAX 5000 |
| Usable Gates | — | 1.25K (approx.) |
| Internal Operating Frequency | — | 62.5 MHz |
| Input Lines | — | 36 |
| Dedicated Inputs | — | 7 |
| Output Lines | — | 28 |
| Programming Technology | — | OTP / UV-Erasable EPROM |
| Programming Interface | — | JTAG (ByteBlaster-compatible) |