EPM5064LC-2 vs EPM5128GC-1 Comparison

Detailed side-by-side comparison of EPM5064LC-2 by Altera and EPM5128GC-1 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM5064LC-2 EPM5128GC-1
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Device Family MAX 5000 —
Product Type CPLD (Complex Programmable Logic Device) —
Macrocells 64 128
Logic Array Blocks (LABs) 4 —
Logic Elements per LAB 16 —
Number of Inputs 36 (7 dedicated + 28 I/O) —
Number of I/O Pins 28 —
Number of Flip-Flops 28 —
Propagation Delay (tPD) 45 ns 16 ns (typical, -1 speed grade)
Maximum Internal Frequency 40 MHz —
Process Technology CMOS, OTP EPROM (UV-erasable base) —
Programmable Polarity Yes —
Programmable Output Enable Yes, per macrocell —
Supply Voltage (VCC) 4.75 V to 5.25 V (5 V nominal) —
Operating Temperature -40 C to +85 C (commercial LC grade) [DATA_NEEDED: explicit min/max in source] -40C to +85C (industrial)
Package PLCC-44 (J-Lead, plastic) PGA-96+ (Pin Grid Array, ceramic windowed)
Mounting Type Surface Mount —
RoHS Status [DATA_NEEDED: not specified in source] [DATA_NEEDED: RoHS compliance - ceramic PGA part is legacy]
Programming Method Altera byte-wide / JTAG programmer UV erase + EPROM program (or device programmer)
Family — MAX 5000
Device Type — UV-erasable CMOS CPLD
Usable Gates — 2,500
Dedicated Inputs — 7
Maximum User I/O Pins — 52
Nominal Supply Voltage — 5 V
Supply Voltage Range — 4.75 V to 5.25 V
Maximum Operating Frequency — 62.5 MHz
Technology — CMOS, UV-erasable EPROM
IOL / IOH — 100 mA / 25 mA per pin (legacy figure, [DATA_NEEDED: verify exact drive spec])
Security Bit — Programmable, prevents readback
MSL Level — [DATA_NEEDED: MSL level]

Datasheets & Resources

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