EPM5064LC-2 vs EPM5128GC-1 比較
詳細並排比較 EPM5064LC-2 由 Altera 與 EPM5128GC-1 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5064LC-2 | EPM5128GC-1 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Device Family | MAX 5000 | — |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 64 | 128 |
| Logic Array Blocks (LABs) | 4 | — |
| Logic Elements per LAB | 16 | — |
| Number of Inputs | 36 (7 dedicated + 28 I/O) | — |
| Number of I/O Pins | 28 | — |
| Number of Flip-Flops | 28 | — |
| Propagation Delay (tPD) | 45 ns | 16 ns (typical, -1 speed grade) |
| Maximum Internal Frequency | 40 MHz | — |
| Process Technology | CMOS, OTP EPROM (UV-erasable base) | — |
| Programmable Polarity | Yes | — |
| Programmable Output Enable | Yes, per macrocell | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | — |
| 工作溫度 | -40 C to +85 C (commercial LC grade) [DATA_NEEDED: explicit min/max in source] | -40C to +85C (industrial) |
| 封裝 | PLCC-44 (J-Lead, plastic) | PGA-96+ (Pin Grid Array, ceramic windowed) |
| 安裝類型 | Surface Mount | — |
| RoHS 狀態 | [DATA_NEEDED: not specified in source] | [DATA_NEEDED: RoHS compliance - ceramic PGA part is legacy] |
| Programming Method | Altera byte-wide / JTAG programmer | UV erase + EPROM program (or device programmer) |
| Family | — | MAX 5000 |
| Device Type | — | UV-erasable CMOS CPLD |
| Usable Gates | — | 2,500 |
| Dedicated Inputs | — | 7 |
| Maximum User I/O Pins | — | 52 |
| Nominal Supply Voltage | — | 5 V |
| Supply Voltage Range | — | 4.75 V to 5.25 V |
| Maximum Operating Frequency | — | 62.5 MHz |
| Technology | — | CMOS, UV-erasable EPROM |
| IOL / IOH | — | 100 mA / 25 mA per pin (legacy figure, [DATA_NEEDED: verify exact drive spec]) |
| Security Bit | — | Programmable, prevents readback |
| MSL 等級 | — | [DATA_NEEDED: MSL level] |