EPM5128GC-1 vs EPM5128JC-1 Comparison
Detailed side-by-side comparison of EPM5128GC-1 by Altera and EPM5128JC-1 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5128GC-1 | EPM5128JC-1 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 |
| Device Type | UV-erasable CMOS CPLD | Erasable Programmable Logic Device (EPLD/CPLD) |
| Macrocells | 128 | 128 |
| Usable Gates | 2,500 | 2,500 |
| Dedicated Inputs | 7 | — |
| Maximum User I/O Pins | 52 | — |
| Nominal Supply Voltage | 5 V | — |
| Supply Voltage Range | 4.75 V to 5.25 V | — |
| Maximum Operating Frequency | 62.5 MHz | 62.5 MHz |
| Propagation Delay (tPD) | 16 ns (typical, -1 speed grade) | — |
| Package | PGA-96+ (Pin Grid Array, ceramic windowed) | 68-pin CQCCJ (Windowed Ceramic J-Lead Chip Carrier) |
| Technology | CMOS, UV-erasable EPROM | CMOS, UV-erasable EPROM |
| Operating Temperature | -40C to +85C (industrial) | [DATA_NEEDED: temperature grade] |
| IOL / IOH | 100 mA / 25 mA per pin (legacy figure, [DATA_NEEDED: verify exact drive spec]) | — |
| Security Bit | Programmable, prevents readback | — |
| Programming Method | UV erase + EPROM program (or device programmer) | — |
| MSL Level | [DATA_NEEDED: MSL level] | — |
| RoHS Status | [DATA_NEEDED: RoHS compliance - ceramic PGA part is legacy] | non_compliant (ceramic windowed package) |
| Logic Array Blocks (LABs) | — | [DATA_NEEDED: LAB count] |
| Pin-to-Pin Propagation Delay (tPD) | — | 40 ns |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (5 V nominal) |
| Mounting Type | — | Surface Mount |
| Programming Interface | — | JTAG / Altera dedicated programmer |
| Configuration Memory | — | Non-volatile EPROM (UV-erasable) |
| Lifecycle Status | — | Obsolete - last-time-buy inventory only |