EPM5128LC-1 vs EPM5128LC2 Comparison
Detailed side-by-side comparison of EPM5128LC-1 by Altera and EPM5128LC2 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5128LC-1 | EPM5128LC2 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Last Time Buy |
| Family | MAX 5000 | MAX 5000 |
| Logic Elements / Macrocells | 128 macrocells | — |
| Number of Usable Gates | [DATA_NEEDED: usable gates] | — |
| Dedicated Inputs | 7 | — |
| Bidirectional I/O Pins | 52 | — |
| Total User I/O | 60 (max) | — |
| Propagation Delay (tpd) | 30 ns | — |
| Supply Voltage (VCC) | 5 V (±10%) | 5 V |
| Process Technology | CMOS EPROM, UV-erasable | CMOS EPROM |
| Programmability | UV-erasable / OTP (windowed package) | — |
| Package Type | 68-pin J-lead ceramic chip carrier (PLCC windowed) | — |
| Operating Temperature | 0C to +70C (commercial) | -40 C to +85 C (extended commercial) |
| JTAG Support | IEEE 1149.1 boundary-scan | — |
| Mounting Type | Surface Mount (J-lead PLCC socket compatible) | Through-Hole / Socketed |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macrocells | — | 128 |
| Logic Array Blocks (LABs) | — | 8 |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| Global Clock Inputs | — | 1 dedicated |
| Propagation Delay (tPD) | — | 45 ns |
| Configuration Memory | — | On-chip EPROM (non-volatile) |
| Boundary Scan | — | JTAG / IEEE 1149.1 |
| Package | — | PGA (Pin Grid Array, ceramic) |