EPM5128LC2 - 128-Macrocell MAX 5000 CPLD, 45ns, 5V | Altera
MPN: EPM5128LC2 ⚠ Last Time Buy| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $33.2 | $332.00 |
| 100 | $28.75 | $2,875.00 |
| 500 | $25.1 | $12,550.00 |
| 1,000 | $22.4 | $22,400.00 |
Drop-in alternatives for EPM5128LC2 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPM5128LC-1
✅ Drop-In✓ In Stock
$8.2 / Unit
View Datasheet →EPM5128GC2
✅ Drop-In✓ In Stock
$54 / Unit
View Datasheet →EPM5128GC-1
✅ Drop-In✓ In Stock
$18.95 / Unit
View Datasheet →EPM5128GC-2
✅ Drop-In✓ In Stock
$8.95 / Unit
View Datasheet →EPM5128JC
✅ Drop-In✓ In Stock
$9.75 / Unit
View Datasheet →EPM5128JC-2
✅ Drop-In✓ In Stock
$21.75 / Unit
View Datasheet →EPM5128LC2 Maximum Ratings & Electrical Characteristics
| Family | MAX 5000 |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Macrocells | 128 |
| Logic Array Blocks (LABs) | 8 |
| Interconnect | Programmable Interconnect Array (PIA) |
| Global Clock Inputs | 1 dedicated |
| Propagation Delay (tPD) | 45 ns |
| Supply Voltage (VCC) | 5 V |
| Process Technology | CMOS EPROM |
| Configuration Memory | On-chip EPROM (non-volatile) |
| Boundary Scan | JTAG / IEEE 1149.1 |
| Operating Temperature | -40 C to +85 C (extended commercial) |
| Package | PGA (Pin Grid Array, ceramic) |
| Mounting Type | Through-Hole / Socketed |
EPM5128LC2 pga (pin grid array, ceramic) Pin Configuration Guide
Complete pinout information for EPM5128LC2 (pga (pin grid array, ceramic) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EPM5128LC2.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM5128LC2 is suitable for 7 applications: TTL/74-Series Glue Logic Consolidation, Address Decoding and Bus Interfacing, State Machine and Sequencer Replacement, Industrial Control I/O Expansion, Legacy Computer Board Repair and Retrofit, Telecommunications Line-Card Glue Logic, Test and Measurement Front-End Logic.
TTL/74-Series Glue Logic Consolidation
The EPM5128LC2 consolidates dozens of 74-series TTL packages (decoders, muxes, latches, AND/OR gates) into a single 128-macrocell CPLD, reducing board area and BOM count in industrial controllers. Its 45 ns pin-to-pin delay matches TTL propagation times so legacy timing budgets remain valid, while the EPROM-based non-volatile configuration eliminates the need for a separate boot PROM and provides instant-on behavior at power-up, critical for deterministic industrial control loops.
Recommended
Address Decoding and Bus Interfacing
The EPM5128LC2 is well suited to legacy address decoding and bus-interface tasks in 8086/80186/68000 CPU systems where its 128 macrocells handle 16- to 24-bit address maps with several chip-select outputs. The deterministic PIA routing produces predictable, fixed propagation delays that simplify worst-case timing analysis for memory and peripheral read/write cycles. The 5 V TTL-compatible I/Os mate directly with industry-standard buses without level shifters.
Recommended
State Machine and Sequencer Replacement
The EPM5128LC2 replaces discrete PAL/GAL sequencers with a single device offering up to 128 macrocells, each with a programmable flip-flop - sufficient for complex multi-state control machines in telecom line cards and test equipment. Its 45 ns tPD plus deterministic PIA routing enables tight state-to-state transitions without metastability concerns, while the EPROM configuration retains the state machine definition through power cycles for instant restart in unattended equipment.
Recommended
Industrial Control I/O Expansion
In PLC-style industrial controllers, the EPM5128LC2 expands a microcontroller's I/O count by handling matrix-key scanning, relay/SSR drivers, optocoupler interfacing, and pulse-width modulation at modest rates. The 5 V supply aligns with industrial 5 V backplanes, the -40 C to +85 C extended commercial range covers factory-floor environments, and the ceramic PGA package supports socketed field replacement to minimize downtime on legacy lines.
Recommended
Legacy Computer Board Repair and Retrofit
The EPM5128LC2 is widely used to repair and retrofit legacy VME, ISA, and Multibus-based computer boards whose original discrete-logic or obsolete PROM-based controllers have become unobtainable. The ceramic PGA package allows socketed replacement, while the EPROM-based non-volatile configuration means a programmed device powers up in the correct state without external boot support. Industrial users keep this part in service for sustaining legacy systems.
Recommended
Telecommunications Line-Card Glue Logic
In telecommunications line cards and channel banks, the EPM5128LC2 implements framing, alarm monitoring, and switch-matrix control logic between the line interface and the central processor. Its 128 macrocells handle several alarm inputs and switch-matrix outputs in a single device, while the deterministic 45 ns delay and 5 V TTL I/O simplify interface to legacy T1/E1 framers. Non-volatile EPROM configuration supports instant-on boot in unattended central-office equipment.
Recommended
Test and Measurement Front-End Logic
Bench-top test instruments and ATE front-ends use the EPM5128LC2 to implement scan-path control, relay-matrix drivers, range switching, and trigger logic. Its 128 macrocells handle complex trigger sequences and matrix addressing without resorting to FPGAs, and the 45 ns delay fits the timing of mid-speed analog multiplexers. The JTAG/IEEE 1149.1 boundary-scan interface simplifies board-level test access during production.
Recommended
Recommended Products Summary
Engineering reference data for EPM5128LC2 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM5128LC-1 | EPM5128GC2 | EPM5128GC-1 | EPM5128GC-2 | EPM5128JC | EPM5128JC-2 |
|---|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | PGA (ceramic) | PGA (ceramic) | PGA (ceramic) | PGA (ceramic) | PGA (ceramic) | PLCC (plastic J-lead) | PLCC (plastic J-lead) |
| Macrocells | 128 | 128 | 128 | 128 | 128 | 128 | 128 |
| Propagation Delay (tPD) | 45 ns | 35 ns | 45 ns | 35 ns | 45 ns | 35 ns | 45 ns |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Temperature Grade | Extended Commercial | Extended Commercial | Wider-Temp Commercial | Wider-Temp Commercial | Wider-Temp Commercial | Commercial (plastic) | Commercial (plastic) |
| Process / Power | Low-power CMOS (L) | Low-power CMOS (L) | Standard CMOS (G) | Standard CMOS (G) | Standard CMOS (G) | Standard CMOS (J) | Standard CMOS (J) |
| Boundary Scan (JTAG) | Yes (IEEE 1149.1) | Yes (IEEE 1149.1) | Yes (IEEE 1149.1) | Yes (IEEE 1149.1) | Yes (IEEE 1149.1) | Yes (IEEE 1149.1) | Yes (IEEE 1149.1) |
| Configuration Memory | EPROM (non-volatile) | EPROM (non-volatile) | EPROM (non-volatile) | EPROM (non-volatile) | EPROM (non-volatile) | EPROM (non-volatile) | EPROM (non-volatile) |
Key Differentiators
- Faster tPD in same ceramic PGA package (vs EPM5128LC-1)
- Low-power CMOS grade for reduced Icc (vs EPM5128GC2)
- Ceramic PGA package for high reliability (vs EPM5128JC)
Design Notes
Estimated: confirm with Altera/Intel before committing to a new design - the MAX 5000 family is classified as mature/last-time-buy, and the EPM5128LC2 is generally available only as excess stock from secondary-market distributors. For new designs, choose MAX 7000, MAX II, MAX V, or Lattice ispMACH 4000 parts to avoid premature obsolescence of the production line.
Use a high-quality PGA socket (e.g., machined-pin) for the ceramic PGA package to allow field replacement, because the ceramic body is brittle and direct soldering risks thermal-crack failures during rework. Provide generous keep-out around the PGA footprint for socket clearance and for the EPROM-programmer clip if you intend to re-program in place.
The MAX 5000 family PIA architecture produces deterministic, fixed propagation delays - this is an advantage for static timing closure in control logic, but the 45 ns tPD is too slow for high-speed memory or bus interfaces above ~20 MHz. For timing-critical paths, choose the faster -1 sub-grade (35 ns tPD) or move to a MAX 7000A/MAX II device.
The 'L' (low-power) grade of the EPM5128LC2 reduces Icc versus the 'G' and 'J' grades, but the EPROM-programming and erase currents during in-system programming are higher than normal operating current. Decouple VCC with a 0.1 uF ceramic plus a 10 uF tantalum placed close to the PGA pins, and reserve programming-current headroom in the 5 V rail design.
Estimated: at 5 V TTL levels, the EPM5128LC2 drives lightly-loaded buses; place termination only if the trace length exceeds ~6 inches or if you switch >50 pF of load. JTAG boundary-scan pins (TDI, TDO, TMS, TCK) must be accessible for production test - route them to a header or test pad rather than to internal-only nets.
Compliance Information
The EPM5128LC2 is a legacy Altera ceramic PGA part; RoHS/REACH/lead-free status is not confirmed in the available web data and is marked as [DATA_NEEDED] in the specs. For production use, request the latest material-composition declaration from the franchised distributor. AEC-Q100 is not applicable because this is a commercial-grade CPLD, not an automotive-qualified part.
