EPM5130JC-1 vs EPM5130JI Comparison
Detailed side-by-side comparison of EPM5130JC-1 by Altera and EPM5130JI by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5130JC-1 | EPM5130JI |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Family | MAX 5000 | MAX 5000 |
| Usable Gates | 2,500 gates | — |
| Macrocells | 128 | 128 |
| Logic Array Blocks (LABs) | 8 | 8 |
| Maximum Operating Frequency | 62.5 MHz | — |
| Propagation Delay (tPD) | 40 ns | 55 ns |
| Supply Voltage (VCC) | 5 V | — |
| Dedicated Inputs | 19 | — |
| I/O Pins | 80 | — |
| Package | 84-pin PLCC (J-lead) | — |
| Mounting Type | Surface Mount | — |
| Programming Technology | UV-erasable EPROM (quartz window) | — |
| Process Technology | CMOS | 0.75 micron CMOS EPROM |
| Operating Temperature | 0C to +70C (commercial) | Commercial (0C to +70C) |
| External Clock Pins | 1 global clock | — |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | Non-compliant (contains Pb in ceramic package) |
| Device Type | — | UV-Erasable EPLD (CMOS EPROM) |
| Maximum Clock Frequency | — | 33.3 MHz |
| External Clock Inputs | — | 1 (shared input/clock) |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| Supply Voltage | — | 5 V (typical) |
| Input Logic Standard | — | TTL-compatible |
| Package Type | — | Ceramic J-Leaded Chip Carrier (JLCC) with UV window |
| Program/Erase Method | — | UV erasure through quartz window |
| Lifecycle | — | Obsolete - EOL by Altera/Intel |