EPM5130JC-1 vs EPM5130LC Comparison
Detailed side-by-side comparison of EPM5130JC-1 by Altera and EPM5130LC by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM5130JC-1
EPM5130JC-1 - 2.5K Gate 128-Macrocell CPLD | Altera/Intel MAX 5000
EPM5130JC-1 ObsoleteSpecification Comparison
| Parameter | EPM5130JC-1 | EPM5130LC |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.25 | $15.60 |
| Product Type | CPLD (Complex Programmable Logic Device) | β |
| Family | MAX 5000 | MAX 5000 (EPM51xx) |
| Usable Gates | 2,500 gates | β |
| Macrocells | 128 | 128 |
| Logic Array Blocks (LABs) | 8 | 8 |
| Maximum Operating Frequency | 62.5 MHz | β |
| Propagation Delay (tPD) | 40 ns | 55 ns |
| Supply Voltage (VCC) | 5 V | 4.5 V to 5.5 V |
| Dedicated Inputs | 19 | 19 |
| I/O Pins | 80 | β |
| Package | 84-pin PLCC (J-lead) | JLCC-68 (J-Lead Ceramic Chip Carrier) |
| Mounting Type | Surface Mount | Surface Mount |
| Programming Technology | UV-erasable EPROM (quartz window) | β |
| Process Technology | CMOS | CMOS (0.7 um EPROM) |
| Operating Temperature | 0C to +70C (commercial) | [DATA_NEEDED: commercial/industrial/military grade] |
| External Clock Pins | 1 global clock | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | Non-compliant (ceramic JLCC, contains lead) |
| Series | β | MAX 5000 |
| User I/O Pins | β | 48 |
| Total Inputs (Dedicated + I/O) | β | 68 |
| Maximum Internal Clock Frequency | β | 50 MHz |
| Global Clock Inputs | β | 1 |
| Configuration Technology | β | UV-Erasable / OTP EPROM |
| I/O Standard | β | TTL-compatible |