EPM5130WC-2 vs EPM5130WC-1 Comparison

Detailed side-by-side comparison of EPM5130WC-2 by Altera and EPM5130WC-1 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM5130WC-2 EPM5130WC-1
Brand Altera Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Device Family MAX 5000 —
Product Type UV-Erasable PLD (CPLD) —
Macrocell Count 128 128
Propagation Delay (tPD) 45 ns —
Supply Voltage (VCC) 4.75 V to 5.25 V —
Operating Temperature 0 °C to 70 °C (Commercial) [DATA_NEEDED: operating temperature range]
Process Technology CMOS CMOS EPROM
Dedicated Inputs 19 —
User I/O Lines 48 —
Total Inputs (I/O + dedicated) 68 —
Package Type 100-terminal Ceramic CQFP (R-CQFP-G100), windowed, gull-wing 100-pin Ceramic QFP (Windowed)
Terminal Pitch 0.650 mm —
Mounting Type Surface Mount Surface Mount
Configuration Memory UV-erasable CMOS EEPROM cells EPROM (on-chip)
Speed Grade -2 (45 ns) —
RoHS Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS compliance]
Lead-Free [DATA_NEEDED: lead-free status] —
Logic Elements AND/OR array with programmable macrocell register —
Series — MAX 5000
Manufacturer — Altera (now Intel)
Device Type — CPLD (Complex Programmable Logic Device)
Logic Array Blocks — Multiple LABs (per MAX 5000 architecture)
Propagation Delay (tpd) — 40 ns
Maximum Clock Frequency — 50 MHz
Erasure Method — UV (ultraviolet, windowed package)
User I/O Pins — Up to 100
Supply Voltage — [DATA_NEEDED: VCC nominal]
Programmable — Yes (UV-erasable, non-volatile)
Logic Family — MAX 5000 (Altera)

Datasheets & Resources

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