EPM5192-1LC vs EPM5128LC-1 Comparison
Detailed side-by-side comparison of EPM5192-1LC by Altera and EPM5128LC-1 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5192-1LC | EPM5128LC-1 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Usable Gates | 3,750 | — |
| Macrocells | 192 | — |
| Logic Array Blocks (LABs) | 4 | — |
| User I/O Pins | 64 | — |
| Maximum Operating Frequency | 62.5 MHz | — |
| Propagation Delay (tpd) | [DATA_NEEDED: -1 speed grade tpd in ns] | 30 ns |
| Supply Voltage | 5 V | — |
| Process Technology | UV EPROM, erasable windowless | CMOS EPROM, UV-erasable |
| Programmable Interconnect | PIA (Programmable Interconnect Array) | — |
| JTAG Boundary Scan | IEEE 1149.1 compliant | — |
| Package | 64-pin Ceramic J-Lead Chip Carrier (LC) | — |
| Mounting Type | Surface Mount | Surface Mount (J-lead PLCC socket compatible) |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (commercial) |
| RoHS Status | Non-compliant (ceramic windowless package, lead-bearing termination) | [DATA_NEEDED: RoHS status] |
| Logic Elements / Macrocells | — | 128 macrocells |
| Number of Usable Gates | — | [DATA_NEEDED: usable gates] |
| Dedicated Inputs | — | 7 |
| Bidirectional I/O Pins | — | 52 |
| Total User I/O | — | 60 (max) |
| Supply Voltage (VCC) | — | 5 V (±10%) |
| Programmability | — | UV-erasable / OTP (windowed package) |
| Package Type | — | 68-pin J-lead ceramic chip carrier (PLCC windowed) |
| JTAG Support | — | IEEE 1149.1 boundary-scan |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |