EPM5192AGC84-20 vs EPM5192AGC-20 Comparison
Detailed side-by-side comparison of EPM5192AGC84-20 by Altera and EPM5192AGC-20 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM5192AGC84-20
EPM5192AGC84-20 - 192-Macrocell MAX 5000 UV PLD | Altera | 84-CPGA
EPM5192AGC84-20 ObsoleteIntel
EPM5192AGC-20
EPM5192AGC-20 - MAX 5000 EPLD, 192 Macrocells | Altera (Intel)
EPM5192AGC-20 ObsoleteSpecification Comparison
| Parameter | EPM5192AGC84-20 | EPM5192AGC-20 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $41.20 | $9.95 |
| Product Type | Complex Programmable Logic Device (CPLD) | β |
| Family | MAX 5000 | MAX 5000 |
| Macrocells | 192 | 192 |
| User I/O Pins | 64 | β |
| Dedicated Inputs | 7 | β |
| Logic Gates (typical) | [DATA_NEEDED: typical gate count] | β |
| Maximum Clock Frequency (fMAX) | 66.7 MHz | β |
| Pin-to-Pin Delay (tPD) | 20 ns | β |
| Speed Grade | -20 | β |
| Package | 84-pin Ceramic Pin Grid Array (CPGA, WPGA) | PGA-132 (ceramic windowed, 'GC') |
| Package Code | WPGA | β |
| Erasure Method | UV-Erasable (with OTP window) | β |
| Process Technology | CMOS | β |
| Operating Temperature Grade | Commercial | β |
| Supply Voltage | [DATA_NEEDED: VCC range] | β |
| I/O Standard | 5V CMOS / TTL compatible | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS status - ceramic PGA windowed parts are typically pre-RoHS] |
| Mounting Type | Through-Hole (Pin Grid Array socket) | Through-hole (PGA socket) |
| Device Type | β | EPLD (EEPLD, UV-erasable) |
| Usable Gates | β | 12,000 |
| Propagation Delay (tPD) | β | 20 ns |
| Counter Frequency (fCNT) | β | 100 MHz (max) |
| Supply Voltage (VCC) | β | 5 V (4.75 V to 5.25 V) |
| Logic Array Blocks (LABs) | β | 8 |
| Dedicated I/O Pins | β | 96 |
| Programming Interface | β | IEEE 1149.1 JTAG |
| In-System Programmability | β | Yes (5 V ISP) |
| Security Bit | β | Yes (pattern read-back protected) |
| Operating Temperature | β | 0C to 70C (commercial) |