EPM5192AGC84-20 vs EPM5192AGC-20 Vergleich
Detaillierter Direktvergleich von EPM5192AGC84-20 von Altera und EPM5192AGC-20 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM5192AGC84-20 | EPM5192AGC-20 |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $41,20 | $9,95 |
| Product Type | Complex Programmable Logic Device (CPLD) | — |
| Family | MAX 5000 | MAX 5000 |
| Macrocells | 192 | 192 |
| User I/O Pins | 64 | — |
| Dedicated Inputs | 7 | — |
| Logic Gates (typical) | [DATA_NEEDED: typical gate count] | — |
| Maximum Clock Frequency (fMAX) | 66.7 MHz | — |
| Pin-to-Pin Delay (tPD) | 20 ns | — |
| Speed Grade | -20 | — |
| Gehäuse | 84-pin Ceramic Pin Grid Array (CPGA, WPGA) | PGA-132 (ceramic windowed, 'GC') |
| Package Code | WPGA | — |
| Erasure Method | UV-Erasable (with OTP window) | — |
| Process Technology | CMOS | — |
| Operating Temperature Grade | Commercial | — |
| Versorgungsspannung | [DATA_NEEDED: VCC range] | — |
| I/O Standard | 5V CMOS / TTL compatible | — |
| RoHS-Status | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS status - ceramic PGA windowed parts are typically pre-RoHS] |
| Montageart | Through-Hole (Pin Grid Array socket) | Through-hole (PGA socket) |
| Device Type | — | EPLD (EEPLD, UV-erasable) |
| Usable Gates | — | 12,000 |
| Propagation Delay (tPD) | — | 20 ns |
| Counter Frequency (fCNT) | — | 100 MHz (max) |
| Supply Voltage (VCC) | — | 5 V (4.75 V to 5.25 V) |
| Logic Array Blocks (LABs) | — | 8 |
| Dedicated I/O Pins | — | 96 |
| Programming Interface | — | IEEE 1149.1 JTAG |
| In-System Programmability | — | Yes (5 V ISP) |
| Security Bit | — | Yes (pattern read-back protected) |
| Betriebstemperatur | — | 0C to 70C (commercial) |