EPM5192AJC-15 vs EPM5192GC-1 Comparison

Detailed side-by-side comparison of EPM5192AJC-15 by Intel and EPM5192GC-1 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM5192AJC-15 EPM5192GC-1
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Nrnd Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $9.85 $17.85
Family MAX 5000 MAX 5000 (Classic)
Device Type EPLD (Erasable Programmable Logic Device) β€”
Macrocells 192 192
Logic Capacity 100% connectivity, sum-of-products PLA architecture β€”
Pin-to-Pin Delay (tPD) 15 ns β€”
Supply Voltage (VCC) 5 V (4.75 V to 5.25 V) 4.75 V to 5.25 V
Operating Temperature 0C to +70C (commercial) [DATA_NEEDED: operating temperature grade]
Package 84-pin PLCC (J-lead, ceramic, non-windowed) 100-pin Ceramic PGA (GC)
Mounting Type Surface Mount Through-Hole (PGA)
Programmability UV-erasable (windowed variant) / One-Time-Programmable β€”
Toolchain MAX+PLUS II β€”
RoHS Status [DATA_NEEDED: RoHS compliance] [DATA_NEEDED: RoHS status]
Pin Count 84 β€”
User I/O Pins [DATA_NEEDED: user I/O count] 64
Speed Grades Available -15, -20, -25 (this part: -15) β€”
Configuration Memory EPROM (UV-erasable) β€”
Logic Type β€” CPLD (Complex Programmable Logic Device)
Usable Gates β€” 3,750
Logic Array Blocks (LABs) β€” 12
Dedicated Inputs β€” 7
Maximum Propagation Delay (tPD) β€” 40 ns
Maximum Frequency (fMAX) β€” 62.5 MHz
Process Technology β€” CMOS, UV-erasable / OTP
Configuration Method β€” UV-Erase / One-Time Programmable
Interconnect β€” Peripheral Interconnect Array (PIA)

Datasheets & Resources

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