EPM5192AJC84-15 vs EPM5192AGC-15 Comparison
Detailed side-by-side comparison of EPM5192AJC84-15 by Altera and EPM5192AGC-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM5192AJC84-15 - MAX 5000 CPLD, 192 Macrocells, 84-pin PLCC | Altera
EPM5192AJC84-15 Obsolete
Specification Comparison
| Parameter | EPM5192AJC84-15 | EPM5192AGC-15 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | MAX 5000 | — |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Macrocells | 192 | 192 |
| Propagation Delay (tpd) | 15 ns | — |
| Maximum Clock Frequency (fMAX) | 83.3 MHz | — |
| Supply Voltage (VCC) | 5 V (single supply) | 5 V |
| Technology | CMOS, UV-erasable EPROM | CMOS, UV-erasable EPROM |
| Package | 84-pin PLCC (J84C) windowed ceramic | Ceramic Pin Grid Array (PGA) |
| Mounting Type | Surface Mount | — |
| Operating Temperature | [DATA_NEEDED: commercial/industrial/military grade] | [DATA_NEEDED: operating temperature range] |
| Programming Method | UV-erase + EPROM programming (windowed package) | UV erase + EPROM program (via Altera programmer) |
| Logic Blocks | 16 Logic Array Blocks (LABs) | — |
| I/O Pins | [DATA_NEEDED: user I/O count] | — |
| RoHS Status | Non-compliant (contains Pb, ceramic windowed package) | [DATA_NEEDED: RoHS status - legacy ceramic PGA typically non-compliant] |
| Process Technology | CMOS EPROM | — |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Series | — | MAX 5000 |
| Logic Array Blocks | — | 16 (typical for 192-macrocell MAX 5000) |
| Maximum User I/O Pins | — | 64 |
| Dedicated Inputs | — | 7 |
| Total Inputs | — | 72 |
| Propagation Delay (tPD) | — | 15 ns (pin-to-pin, -15 speed grade) |
| Lifecycle Status | — | Obsolete / Last Time Buy (per Altera legacy product list) |