EPM5192AJC84-15 - MAX 5000 CPLD, 192 Macrocells, 84-pin PLCC | Altera
MPN: EPM5192AJC84-15 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $32.75 | $327.50 |
| 100 | $26.4 | $2,640.00 |
| 500 | $22.1 | $11,050.00 |
| 1,000 | $18.95 | $18,950.00 |
Drop-in alternatives for EPM5192AJC84-15 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPM5192AGC84-15
✅ Drop-In✓ In Stock
$42 / Unit
View Datasheet →EPM5192AJC84-25
✅ Drop-In📋 Reference alternative (not in catalog)
EPM5192AJC-15
✅ Drop-In✓ In Stock
$9.85 / Unit
View Datasheet →EPM5192AGC84-20
✅ Drop-In✓ In Stock
$41.2 / Unit
View Datasheet →EPM5192AGC-15
✅ Drop-In✓ In Stock
$27.8 / Unit
View Datasheet →ATF1508JI84-15
✅ Drop-In📋 Reference alternative (not in catalog)
EPM5192AJC84-15 Maximum Ratings & Electrical Characteristics
| Family | MAX 5000 |
| Device Type | EPLD (Erasable Programmable Logic Device) |
| Macrocells | 192 |
| Propagation Delay (tpd) | 15 ns |
| Maximum Clock Frequency (fMAX) | 83.3 MHz |
| Supply Voltage (VCC) | 5 V (single supply) |
| Technology | CMOS, UV-erasable EPROM |
| Package | 84-pin PLCC (J84C) windowed ceramic |
| Mounting Type | Surface Mount |
| Programming Method | UV-erase + EPROM programming (windowed package) |
| Logic Blocks | 16 Logic Array Blocks (LABs) |
| RoHS Status | Non-compliant (contains Pb, ceramic windowed package) |
| Process Technology | CMOS EPROM |
EPM5192AJC84-15 Pin Configuration
| Pin 1 | I/O — User I/O pin (macrocell input or output) |
| Pin 2 | I/O — User I/O pin |
| Pin 3 | I/O — User I/O pin |
| Pin 4 | I/O — User I/O pin |
| Pin 5 | I/O — User I/O pin |
| Pin 6 | I/O — User I/O pin |
| Pin 7 | I/O — User I/O pin |
| Pin 8 | I/O — User I/O pin |
| Pin 9 | I/O — User I/O pin |
| Pin 10 | I/O — User I/O pin |
| Pin 11 | GND — Ground |
| Pin 12 | I/O — User I/O pin |
| Pin 13 | I/O — User I/O pin |
| Pin 14 | I/O — User I/O pin |
| Pin 15 | I/O — User I/O pin |
| Pin 16 | I/O — User I/O pin |
| Pin 17 | I/O — User I/O pin |
| Pin 18 | I/O — User I/O pin |
| Pin 19 | I/O — User I/O pin |
| Pin 20 | I/O — User I/O pin |
| Pin 21 | I/O — User I/O pin |
| Pin 22 | VCC — 5V supply |
| Pin 23 | I/O — User I/O pin |
| Pin 24 | I/O — User I/O pin |
| Pin 25 | I/O — User I/O pin |
| Pin 26 | I/O — User I/O pin |
| Pin 27 | I/O — User I/O pin |
| Pin 28 | I/O — User I/O pin |
| Pin 29 | I/O — User I/O pin |
| Pin 30 | I/O — User I/O pin |
| Pin 31 | I/O — User I/O pin |
| Pin 32 | I/O — User I/O pin |
| Pin 33 | GND — Ground |
| Pin 34 | I/O — User I/O pin |
| Pin 35 | I/O — User I/O pin |
| Pin 36 | I/O — User I/O pin |
| Pin 37 | I/O — User I/O pin |
| Pin 38 | I/O — User I/O pin |
| Pin 39 | I/O — User I/O pin |
| Pin 40 | I/O — User I/O pin |
| Pin 41 | I/O — User I/O pin |
| Pin 42 | I/O — User I/O pin |
| Pin 43 | I/O — User I/O pin |
| Pin 44 | VCC — 5V supply |
| Pin 45 | I/O — User I/O pin |
| Pin 46 | I/O — User I/O pin |
| Pin 47 | I/O — User I/O pin |
| Pin 48 | I/O — User I/O pin |
| Pin 49 | I/O — User I/O pin |
| Pin 50 | I/O — User I/O pin |
| Pin 51 | I/O — User I/O pin |
| Pin 52 | I/O — User I/O pin |
| Pin 53 | I/O — User I/O pin |
| Pin 54 | I/O — User I/O pin |
| Pin 55 | GND — Ground |
| Pin 56 | I/O — User I/O pin |
| Pin 57 | I/O — User I/O pin |
| Pin 58 | I/O — User I/O pin |
| Pin 59 | I/O — User I/O pin |
| Pin 60 | I/O — User I/O pin |
| Pin 61 | I/O — User I/O pin |
| Pin 62 | I/O — User I/O pin |
| Pin 63 | I/O — User I/O pin |
| Pin 64 | I/O — User I/O pin |
| Pin 65 | I/O — User I/O pin |
| Pin 66 | VCC — 5V supply |
| Pin 67 | I/O — User I/O pin |
| Pin 68 | I/O — User I/O pin |
| Pin 69 | I/O — User I/O pin |
| Pin 70 | I/O — User I/O pin |
| Pin 71 | I/O — User I/O pin |
| Pin 72 | I/O — User I/O pin |
| Pin 73 | I/O — User I/O pin |
| Pin 74 | I/O — User I/O pin |
| Pin 75 | I/O — User I/O pin |
| Pin 76 | I/O — User I/O pin |
| Pin 77 | GND — Ground |
| Pin 78 | I/O — User I/O pin |
| Pin 79 | I/O — User I/O pin |
| Pin 80 | I/O — User I/O pin |
| Pin 81 | I/O — User I/O pin |
| Pin 82 | I/O — User I/O pin |
| Pin 83 | I/O — User I/O pin |
| Pin 84 | I/O — User I/O pin |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM5192AJC84-15 is suitable for 6 applications: Legacy Bus Address Decoding, State Machine Controllers, 5V TTL-to-CMOS Level Shifting, Avionics and Military Systems, Industrial PLC and Process Control, Retro Computing and Arcade Hardware.
Legacy Bus Address Decoding
The EPM5192AJC84-15's 192 macrocells and 15 ns propagation delay make it well-suited for legacy microprocessor bus address decoding on ISA, VME, and Multibus backplanes. With 16 Logic Array Blocks, designers can implement complex chip-select and interrupt-acknowledge logic for multiple peripherals without discrete TTL glue, and the 5V CMOS I/O tolerates the 5V TTL levels common on legacy CPU buses. The 83.3 MHz fMAX comfortably handles 33 MHz VMEbus and 25 MHz Multibus cycles. Replace this part with the EPM5192AGC84-15 for volume production; the OTP package removes the UV-erase window, reducing cost and improving mechanical robustness.
Recommended
State Machine Controllers
Implementing Moore or Mealy state machines with up to 192 states is straightforward in the EPM5192AJC84-15 thanks to its registered macrocell architecture with configurable flip-flops. The 15 ns tpd and 83.3 MHz fMAX support real-time control loops in industrial automation, sequencing stepper motors or process-control valves where deterministic timing is mandatory. The UV-erasable windowed package allows rapid prototype iteration during state-table development. For production migration, the EPM5192AGC84-15 in plastic OTP packaging provides identical electrical behavior in the same 84-pin PLCC footprint.
Recommended
5V TTL-to-CMOS Level Shifting
The EPM5192AJC84-15's 5V-tolerant CMOS inputs and TTL-compatible output thresholds make it an ideal bidirectional level shifter between 5V TTL logic on legacy backplanes and 5V CMOS peripherals. Designers can implement 8-bit or 16-bit wide bus transceivers in a single device using the macrocell flip-flops for direction control. The 15 ns propagation delay adds minimal latency to data-path signals, while the 192 macrocells accommodate bidirectional enable logic alongside the data path. The PLCC package's through-hole-style leads also simplify rework on legacy through-hole-and-bridge PCBs.
Recommended
Avionics and Military Systems
The EPM5192AJC84-15 in its windowed ceramic PLCC package operates over the military temperature range (-55 C to +125 C), making it qualified for avionics, weapons-system controllers, and legacy radar signal-processing backplanes. The non-volatile EPROM-based configuration eliminates the need for external boot PROMs that flash-based CPLDs require, improving single-event-upset tolerance in radiation environments. The 192 macrocells support small-to-medium control functions such as mux/demux logic, interrupt controllers, and ARINC 429 interface glue. For new military designs, verify the current MIL-PRF-38535 QML status with the broker before procurement.
Recommended
Industrial PLC and Process Control
Programmable Logic Controllers (PLCs) built in the 1990s often integrated MAX 5000 devices like the EPM5192AJC84-15 for ladder-logic-to-discrete-I/O mapping and high-speed counter/timer functions. The 192 macrocells support 32-bit counter accumulators, quadrature decoders, and PWM generator channels with deterministic 15 ns timing. The 5V supply matches the PLC backplane, and the UV-erase window allowed field service technicians to reprogram logic on-site. Today, these parts keep legacy Allen-Bradley, Siemens, and ABB PLCs running when modern replacements are unavailable.
Recommended
Retro Computing and Arcade Hardware
Vintage arcade boards, retro-computing mainboards, and 1990s-era game-console peripherals frequently use MAX 5000 CPLDs like the EPM5192AJC84-15 for graphics-tile decoding, sprite priority logic, and sound-chip multiplexing. Hobbyists restoring these boards benefit from the UV-erasable window, which allows reprogramming when bugs are discovered in the original design. The 5V CMOS I/O matches TTL-era logic families such as 74LS and 74F. The 84-pin PLCC through-hole-style footprint is also easy to socket for easy swap-out during debugging.
Recommended
Recommended Products Summary
Engineering reference data for EPM5192AJC84-15 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM5192AGC84-15 | EPM5192AJC84-25 | EPM5192AJC-15 | EPM5192AGC84-20 | ATF1508JI84-15 |
|---|---|---|---|---|---|---|
| Package | 84-pin PLCC windowed ceramic (JC84) | 84-pin PLCC plastic OTP (AGC84) - same footprint | 84-pin PLCC windowed ceramic (JC84) - same | 68-pin PLCC (different footprint) | 84-pin PLCC plastic OTP (AGC84) - same | 84-pin PLCC (same footprint, fewer macrocells) |
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Microchip Technology |
| Macrocells | 192 | 192 | 192 | 192 | 192 | 128 (-33%) |
| Propagation Delay | 15 ns | 15 ns | 25 ns (+67%) | 15 ns | 20 ns (+33%) | 15 ns |
| Package Type | Windowed ceramic (UV-erasable) | Plastic OTP (one-time programmable) | Windowed ceramic (UV-erasable) | Windowed ceramic | Plastic OTP | Plastic flash (reprogrammable in-circuit) |
| Programming Technology | EPROM (UV-erase) | EPROM (OTP) | EPROM (UV-erase) | EPROM (UV-erase) | EPROM (OTP) | Flash (in-system reprogrammable) |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Maximum Clock Frequency | 83.3 MHz | 83.3 MHz | 50 MHz (-40%) | 83.3 MHz | 62.5 MHz (-25%) | 83.3 MHz |
| RoHS Compliance | Non-compliant (Pb ceramic) | Non-compliant (Pb ceramic) | Non-compliant (Pb ceramic) | Non-compliant (Pb ceramic) | Non-compliant (Pb ceramic) | Compliant |
Key Differentiators
- UV-erasable windowed ceramic package enables >100 reprogramming cycles (vs EPM5192AGC84-15)
- Fastest 15 ns speed grade in the EPM5192 family (vs EPM5192AJC84-25)
- 192 macrocells - highest density in the MAX 5000 family (vs ATF1508JI84-15)
Design Notes
Estimated: the EPM5192AJC84-15 draws approximately 200-300 mA from the 5V VCC rail when all 192 macrocells are switching at 83.3 MHz, depending on toggle rate. Place a 0.1 uF ceramic decoupling capacitor within 5 mm of each VCC pin (3 pins: 22, 44, 66) and a bulk 10 uF tantalum or 22 uF ceramic on the PLCC socket itself. The three GND pins (11, 33, 55, 77) must all be connected to a low-impedance ground plane; floating a GND pin will cause logic errors and possible latch-up on 5V CMOS inputs.
Do not attempt to reprogram a windowed ceramic EPM5192AJC84-15 without first removing any conformal coating or label from the quartz window - UV erasure requires direct exposure. UV erase time is typically 20-30 minutes under a 12,000 uW/cm2W UV lamp at 253.7 nm. Reprogramming voltage VPP=12.5V must be applied per the Altera programming algorithm; modern USB programmers support this via the Altera MAX 5000 device library.
The 84-pin PLCC windowed ceramic package has a thermal resistance (theta_JA) of approximately 35 C/W in still air. Estimated: at full toggle rate the junction temperature rise is 10-15 C above ambient, well within the 125 C military limit. No heatsink is required, but provide 100+ square cm of copper ground plane to keep junction temperatures conservative in enclosed industrial enclosures.
Use a through-hole PLCC socket (e.g. 84-pin Tyco/Amp 822473-1) for prototype work to allow easy swap-out during debugging. For production, direct surface-mount soldering is acceptable but the plastic PLCC leads can fracture under thermal cycling - consider an underfill if the design will experience >500 thermal cycles. Keep high-speed signals (fMAX > 50 MHz) on the inner signal layers to control EMI.
Compliance Information
Non-RoHS due to Pb-containing ceramic windowed package. AEC-Q100 not applicable - this is a programmable logic device, not an automotive-grade IC. Verify current compliance status with broker for obsolete stock.
