EPM5192AJC84-15 vs EPM5192AJC84-20 Comparison
Detailed side-by-side comparison of EPM5192AJC84-15 by Altera and EPM5192AJC84-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM5192AJC84-15 - MAX 5000 CPLD, 192 Macrocells, 84-pin PLCC | Altera
EPM5192AJC84-15 ObsoleteAltera
EPM5192AJC84-20 - 192-Macrocell UV PLD, 33ns, 84-Pin J-Lead | Altera
EPM5192AJC84-20 ObsoleteSpecification Comparison
| Parameter | EPM5192AJC84-15 | EPM5192AJC84-20 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD (Erasable Programmable Logic Device) | UV-erasable/OTP Complex PLD (CPLD) |
| Macrocells | 192 | 192 |
| Propagation Delay (tpd) | 15 ns | 33 ns (speed grade -20) |
| Maximum Clock Frequency (fMAX) | 83.3 MHz | — |
| Supply Voltage (VCC) | 5 V (single supply) | — |
| Technology | CMOS, UV-erasable EPROM | — |
| Package | 84-pin PLCC (J84C) windowed ceramic | 84-pin PLCC J-Lead (WQCCJ, J84) |
| Mounting Type | Surface Mount | Surface Mount (J-Lead) |
| Operating Temperature | [DATA_NEEDED: commercial/industrial/military grade] | — |
| Programming Method | UV-erase + EPROM programming (windowed package) | — |
| Logic Blocks | 16 Logic Array Blocks (LABs) | — |
| I/O Pins | [DATA_NEEDED: user I/O count] | — |
| RoHS Status | Non-compliant (contains Pb, ceramic windowed package) | [DATA_NEEDED: RoHS status] |
| Process Technology | CMOS EPROM | CMOS, UV-erasable EEPROM |
| Maximum Clock Frequency | — | 66.7 MHz |
| Supply Voltage (Vcc) | — | 4.75 V to 5.25 V |
| Dedicated Inputs | — | 7 |
| User I/O Lines | — | 64 |
| Operating Temperature Grade | — | Commercial |
| MSL Level | — | [DATA_NEEDED: MSL level] |
| Programming Tool | — | Altera MAX+PLUS II / Quartus (legacy) |
| Lead-Free / Halogen-Free | — | [DATA_NEEDED: lead-free status] |