EPM5192AJC84-20 vs EPM5192ALI84-20 Comparison

Detailed side-by-side comparison of EPM5192AJC84-20 by Altera and EPM5192ALI84-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM5192AJC84-20 EPM5192ALI84-20
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Family MAX 5000 MAX 5000
Device Type UV-erasable/OTP Complex PLD (CPLD) EPLD (UV-erasable / OTP Complex PLD)
Macrocells 192 192
Propagation Delay (tpd) 33 ns (speed grade -20) —
Maximum Clock Frequency 66.7 MHz —
Supply Voltage (Vcc) 4.75 V to 5.25 V —
Dedicated Inputs 7 —
User I/O Lines 64 —
Process Technology CMOS, UV-erasable EEPROM CMOS, EPROM-based
Package 84-pin PLCC J-Lead (WQCCJ, J84) —
Operating Temperature Grade Commercial Industrial (I)
Mounting Type Surface Mount (J-Lead) Surface Mount (PLCC socket compatible)
MSL Level [DATA_NEEDED: MSL level] —
RoHS Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status - Altera MAX 5000 series is generally legacy and may not be RoHS compliant]
Programming Tool Altera MAX+PLUS II / Quartus (legacy) —
Lead-Free / Halogen-Free [DATA_NEEDED: lead-free status] —
Propagation Delay (tPD) — 20 ns (pin-compatible speed grade)
User I/O Pins (max) — 84 (in PLCC-84 package)
Supply Voltage — 5 V (single supply, TTL-compatible I/O)
Package Code — QCCJ (Plastic Leaded Chip Carrier, J-bend)
Package Type — PLCC-84 (PQCC-84)
No. of Terminals — 84
Form of Terminal — J-BEND
Programmability — UV-erasable / one-time programmable (OTP)
Logic Type — Combinatorial and registered, per-macrocell DFF
I/O Standard — TTL-compatible

Datasheets & Resources

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