EPM5192AJI84-20 vs EPM5192AGC84-20 Comparison
Detailed side-by-side comparison of EPM5192AJI84-20 by Altera and EPM5192AGC84-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5192AJI84-20 | EPM5192AGC84-20 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Device Family | MAX 5000 (EPM5192) | — |
| Logic Cells / Macrocells | 192 macrocells | — |
| Device Type | UV-Erasable / OTP Complex PLD | — |
| Propagation Delay (tPD) | 33 ns | — |
| Maximum Frequency (fCNT) | 66.7 MHz | — |
| Supply Voltage (VCC) | 5 V nominal (4.5 V to 5.5 V) | — |
| Process Technology | CMOS | CMOS |
| Operating Temperature Grade | Industrial | Commercial |
| Package Code | WQCCJ (JEDEC) | WPGA |
| Package Type | 84-pin J-bend Ceramic Chip Carrier (PLCC-84, JI) | — |
| Mounting Type | Surface Mount | Through-Hole (Pin Grid Array socket) |
| Terminal Form | J-Bend | — |
| Number of Terminals | 84 | — |
| Programmability | UV-erasable window + OTP | — |
| Pin Count | 84 | — |
| Lifecycle Status | Obsolete (legacy Altera MAX 5000) | — |
| RoHS Status | [DATA_NEEDED: RoHS status of EPM5192AJI84-20] | [DATA_NEEDED: RoHS compliance] |
| Product Type | — | Complex Programmable Logic Device (CPLD) |
| Family | — | MAX 5000 |
| Macrocells | — | 192 |
| User I/O Pins | — | 64 |
| Dedicated Inputs | — | 7 |
| Logic Gates (typical) | — | [DATA_NEEDED: typical gate count] |
| Maximum Clock Frequency (fMAX) | — | 66.7 MHz |
| Pin-to-Pin Delay (tPD) | — | 20 ns |
| Speed Grade | — | -20 |
| Package | — | 84-pin Ceramic Pin Grid Array (CPGA, WPGA) |
| Erasure Method | — | UV-Erasable (with OTP window) |
| Supply Voltage | — | [DATA_NEEDED: VCC range] |
| I/O Standard | — | 5V CMOS / TTL compatible |