EPM5192AJI84-20 vs EPM5192AGC84-20 比較
詳細な並列比較: EPM5192AJI84-20 メーカー: Altera および EPM5192AGC84-20 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM5192AJI84-20 | EPM5192AGC84-20 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $10.95 | $41.20 |
| Device Family | MAX 5000 (EPM5192) | — |
| Logic Cells / Macrocells | 192 macrocells | — |
| Device Type | UV-Erasable / OTP Complex PLD | — |
| Propagation Delay (tPD) | 33 ns | — |
| Maximum Frequency (fCNT) | 66.7 MHz | — |
| Supply Voltage (VCC) | 5 V nominal (4.5 V to 5.5 V) | — |
| Process Technology | CMOS | CMOS |
| Operating Temperature Grade | Industrial | Commercial |
| Package Code | WQCCJ (JEDEC) | WPGA |
| Package Type | 84-pin J-bend Ceramic Chip Carrier (PLCC-84, JI) | — |
| 実装タイプ | Surface Mount | Through-Hole (Pin Grid Array socket) |
| Terminal Form | J-Bend | — |
| Number of Terminals | 84 | — |
| Programmability | UV-erasable window + OTP | — |
| ピン数 | 84 | — |
| ライフサイクル状態 | Obsolete (legacy Altera MAX 5000) | — |
| RoHS ステータス | [DATA_NEEDED: RoHS status of EPM5192AJI84-20] | [DATA_NEEDED: RoHS compliance] |
| Product Type | — | Complex Programmable Logic Device (CPLD) |
| Family | — | MAX 5000 |
| Macrocells | — | 192 |
| User I/O Pins | — | 64 |
| Dedicated Inputs | — | 7 |
| Logic Gates (typical) | — | [DATA_NEEDED: typical gate count] |
| Maximum Clock Frequency (fMAX) | — | 66.7 MHz |
| Pin-to-Pin Delay (tPD) | — | 20 ns |
| Speed Grade | — | -20 |
| パッケージ | — | 84-pin Ceramic Pin Grid Array (CPGA, WPGA) |
| Erasure Method | — | UV-Erasable (with OTP window) |
| 電源電圧 | — | [DATA_NEEDED: VCC range] |
| I/O Standard | — | 5V CMOS / TTL compatible |