EPM5192ALC84-20 vs EPM5192ALI84-20 Comparison

Detailed side-by-side comparison of EPM5192ALC84-20 by Altera and EPM5192ALI84-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM5192ALC84-20 EPM5192ALI84-20
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Device Type UV-Erasable/OTP Complex PLD (EPLD) EPLD (UV-erasable / OTP Complex PLD)
Series Altera MAX 5000 —
Macrocells 192 192
Process Technology CMOS CMOS, EPROM-based
Speed Grade -20 (20 ns pin-to-pin delay) —
Package 84-pin PLCC (Plastic Leaded Chip Carrier) —
Terminal Pitch 1.270 mm —
Terminal Form J-bend —
Package Code QCCJ (PLCC-84) QCCJ (Plastic Leaded Chip Carrier, J-bend)
Package Shape Square —
Temperature Grade Commercial —
Programming Method UV-erase + EPROM (One-Time-Programmable option) —
Logic Family MAX 5000 EPLD —
I/O Compatibility TTL-compatible —
Mounting Type Surface Mount (PLCC socket-compatible) Surface Mount (PLCC socket compatible)
Configuration Memory EPROM (UV-erasable) —
RoHS Status [DATA_NEEDED: RoHS status not in provided web data] [DATA_NEEDED: RoHS status - Altera MAX 5000 series is generally legacy and may not be RoHS compliant]
Family — MAX 5000
Propagation Delay (tPD) — 20 ns (pin-compatible speed grade)
User I/O Pins (max) — 84 (in PLCC-84 package)
Supply Voltage — 5 V (single supply, TTL-compatible I/O)
Operating Temperature Grade — Industrial (I)
Package Type — PLCC-84 (PQCC-84)
No. of Terminals — 84
Form of Terminal — J-BEND
Programmability — UV-erasable / one-time programmable (OTP)
Logic Type — Combinatorial and registered, per-macrocell DFF
I/O Standard — TTL-compatible

Datasheets & Resources

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