EPM5192ALI84-15 vs EPM5192ALI84-20 Comparison

Detailed side-by-side comparison of EPM5192ALI84-15 by Altera and EPM5192ALI84-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM5192ALI84-15 EPM5192ALI84-20
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Device Family MAX 5000 —
Product Type UV-Erasable / OTP Complex PLD —
Logic Macrocells 192 —
Dedicated Inputs 7 —
Bidirectional I/O Pins 64 —
Maximum Total Inputs 72 —
Propagation Delay (tPD) 25 ns (-15 speed grade) 20 ns (pin-compatible speed grade)
Process Technology CMOS, non-volatile EPROM/OTP CMOS, EPROM-based
Programmability One-Time Programmable (windowless) UV-erasable / one-time programmable (OTP)
Package 84-pin PQCC (PLCC, J-Lead) —
JEDEC JESD-30 Code S-PQCC-J84 —
Terminal Form J Bend (J-Lead) —
Operating Temperature Grade Industrial Industrial (I)
Operating Temperature Range [DATA_NEEDED: temperature range] —
Supply Voltage [DATA_NEEDED: VCC range] 5 V (single supply, TTL-compatible I/O)
Mounting Type Surface Mount (PLCC socket compatible) Surface Mount (PLCC socket compatible)
RoHS Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status - Altera MAX 5000 series is generally legacy and may not be RoHS compliant]
Family — MAX 5000
Device Type — EPLD (UV-erasable / OTP Complex PLD)
Macrocells — 192
User I/O Pins (max) — 84 (in PLCC-84 package)
Package Code — QCCJ (Plastic Leaded Chip Carrier, J-bend)
Package Type — PLCC-84 (PQCC-84)
No. of Terminals — 84
Form of Terminal — J-BEND
Logic Type — Combinatorial and registered, per-macrocell DFF
I/O Standard — TTL-compatible

Datasheets & Resources

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