EPM5192ALI84-15 - 192-Macrocell OTP PLD, 84-PQCC | Altera
MPN: EPM5192ALI84-15 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.85 | $1,385.00 |
| 500 | $11.4 | $5,700.00 |
| 1,000 | $9.95 | $9,950.00 |
Drop-in alternatives for EPM5192ALI84-15 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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EPM5192ALI84-20
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$9.9 / Unit
View Datasheet βEPM5192ALC84-15
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$13.2 / Unit
View Datasheet βEPM5192ALC84-20
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$19.4 / Unit
View Datasheet βEPM5192AJI84-15
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$27.8 / Unit
View Datasheet βEPM5192AJI84-20
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$10.95 / Unit
View Datasheet βEPM5192ALI84-15 Maximum Ratings & Electrical Characteristics
| Device Family | MAX 5000 |
| Product Type | UV-Erasable / OTP Complex PLD |
| Logic Macrocells | 192 |
| Dedicated Inputs | 7 |
| Bidirectional I/O Pins | 64 |
| Maximum Total Inputs | 72 |
| Propagation Delay (tPD) | 25 ns (-15 speed grade) |
| Process Technology | CMOS, non-volatile EPROM/OTP |
| Programmability | One-Time Programmable (windowless) |
| Package | 84-pin PQCC (PLCC, J-Lead) |
| JEDEC JESD-30 Code | S-PQCC-J84 |
| Terminal Form | J Bend (J-Lead) |
| Operating Temperature Grade | Industrial |
| Mounting Type | Surface Mount (PLCC socket compatible) |
EPM5192ALI84-15 Pin Configuration
| Pin 1 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 2 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 3 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 4 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 5 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 6 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 7 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 8 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 9 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 10 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 11 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 12 | GND β Ground |
| Pin 13 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 14 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 15 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 16 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 17 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 18 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 19 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 20 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 21 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 22 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 23 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 24 | VCC β Supply voltage |
| Pin 25 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 26 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 27 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 28 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 29 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 30 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 31 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 32 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 33 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 34 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 35 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 36 | GND β Ground |
| Pin 37 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 38 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 39 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 40 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 41 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 42 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 43 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 44 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 45 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 46 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 47 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 48 | VCC β Supply voltage |
| Pin 49 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 50 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 51 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 52 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 53 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 54 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 55 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 56 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 57 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 58 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 59 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 60 | GND β Ground |
| Pin 61 | INPUT/GCLK β Dedicated input or global clock |
| Pin 62 | INPUT/OE β Dedicated input or output enable |
| Pin 63 | INPUT β Dedicated input |
| Pin 64 | INPUT β Dedicated input |
| Pin 65 | INPUT β Dedicated input |
| Pin 66 | INPUT β Dedicated input |
| Pin 67 | INPUT β Dedicated input |
| Pin 68 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 69 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 70 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 71 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 72 | VCC β Supply voltage |
| Pin 73 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 74 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 75 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 76 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 77 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 78 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 79 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 80 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 81 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 82 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 83 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 84 | I/O β Bidirectional I/O pin (macrocell) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM5192ALI84-15 is suitable for 6 applications: Legacy Microprocessor Glue Logic, Industrial Controller Address Decoding, State Machine Integration, VMEbus / Multibus Interface Logic, 7400-Series TTL Replacement, Legacy Equipment Repair and Sustaining.
Legacy Microprocessor Glue Logic
The EPM5192ALI84-15's 192 macrocells and 25 ns propagation delay suit legacy 8/16/20 MHz microprocessor bus-interface glue logic. In systems using 80C186, 68k, or Z80 processors, it consolidates address decoding, wait-state generation, chip-select logic, and interrupt prioritization into a single 84-PLCC, replacing 5-10 discrete 74LS/74F PAL/GAL devices. The windowless OTP architecture is ideal for production units where the design is finalized - prototype builds can use the windowed LC84 variant for UV-erase iterations. The 72-input capacity accommodates the full 20-bit address bus plus control signals. Migration to modern MAX II/MAX V CPLDs is recommended for new designs requiring Flash reprogrammability.
Recommended
Industrial Controller Address Decoding
In industrial PLC and process-control backplanes, the EPM5192ALI84-15 provides reliable address decoding for I/O expansion modules and memory-mapped peripherals. The 192-macrocell capacity supports up to 192 independent chip-select or enable signals, while the 25 ns tPD maintains timing margin with ISA bus cycles (~120 ns minimum) and VMEbus. The industrial temperature grade (-40C to 85C) tolerates factory-floor environments. The 84-pin PQCC package is socket-compatible for field replacement in legacy installations - critical for industrial systems with 20+ year service lives where the original Altera PLDs must be replaced as they reach end-of-life. No cross-brand equivalent shares the 84-PLCC footprint.
Recommended
State Machine Integration
The EPM5192ALI84-15 is well suited to large state-machine integration in control panels, where multiple discrete TTL state machines need to be consolidated into one device. Each of the 192 macrocells can implement a registered state bit with combinatorial next-state logic, supporting FSMs with 50+ states and complex transition graphs. The OTP programming is appropriate for production units once the FSM is validated, while the 25 ns tPD enables state transitions at up to ~20 MHz. The 64 I/O pins interface directly to 5V logic. Designers should note that the OTP architecture prevents in-system reprogramming - design changes require a new programmed part, so prototype with the windowed LC84 variant before committing to OTP.
Recommended
VMEbus / Multibus Interface Logic
In VMEbus and Multibus backplane systems, the EPM5192ALI84-15 implements bus arbitration, interrupt acknowledge, and address-modifier decoding with timing that meets the 25 ns bus-signal requirements. The 192 macrocells support multiple parallel arbitration schemes, while the 7 dedicated inputs accept bus-grant and request signals. The PQCC-84 package and CMOS EPROM technology have proven reliability in long-lifecycle aerospace, defense, and industrial VME installations. For new VME designs, consider the MAX II EPM240 or MAX V EPM570, but for legacy VME backplane repair, the EPM5192ALI84-15 remains the original-fit part. The industrial temperature grade tolerates chassis-internal temperatures up to 85C.
Recommended
7400-Series TTL Replacement
The EPM5192ALI84-15 is a one-for-many replacement for 7400-series TTL glue logic in legacy through-hole designs. A single EPM5192ALI84-15 typically replaces 10-20 discrete 74LS/74F/74AS chips (decoders, multiplexers, latches, parity generators, comparators), reducing board area, power consumption, and BOM cost. The OTP programming is well-suited to designs where the glue logic is finalized and replicated across many production units. The 84-PLCC footprint fits on legacy boards designed around DIP-20/24 sockets with adapter boards. For new TTL-replacement designs, evaluate the EPM240 (MAX II) which provides similar density in a smaller TQFP-100 package with Flash reprogrammability.
Recommended
Legacy Equipment Repair and Sustaining
The primary modern use of the EPM5192ALI84-15 is sustaining engineering for legacy equipment with installed bases of 20+ years. Aerospace test equipment, military radios, industrial process controllers, and scientific instruments originally designed in the 1990s use this PLD as glue logic. When a unit fails in the field, a replacement programmed EPM5192ALI84-15 can be socketed in directly - the PQCC-84 form factor uses standard test-burn-in sockets available from 3M, Yamaichi, and Wells-CTI. Independent distributors (Jotrin, Microchip USA, FPGAkey) maintain limited stock. For new equipment, MAX II/MAX V CPLDs are the recommended replacement path, but the EPM5192ALI84-15 remains irreplaceable for legacy repair.
Recommended
Recommended Products Summary
Engineering reference data for EPM5192ALI84-15 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM5192ALI84-20 | EPM5192ALC84-15 | EPM5192ALC84-20 | EPM5192AJI84-15 | EPM5192AJI84-20 |
|---|---|---|---|---|---|---|
| Package | 84-pin PQCC (PLCC, J-Lead) | 84-pin PQCC (PLCC, J-Lead) - same | 84-pin PQCC (PLCC, J-Lead) - same | 84-pin PQCC (PLCC, J-Lead) - same | 84-pin PQCC (PLCC, J-Lead) - same | 84-pin PQCC (PLCC, J-Lead) - same |
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Logic Macrocells | 192 | 192 | 192 | 192 | 192 | 192 |
| Propagation Delay (tPD) | 25 ns (-15 speed grade) | 20 ns (-20 grade, faster) | 25 ns (-15 grade) | 20 ns (-20 grade) | 25 ns (-15 grade) | 20 ns (-20 grade) |
| Temperature Grade | Industrial (-40C to 85C) | Industrial | Commercial (0C to 70C) | Commercial (0C to 70C) | Military (-55C to 125C) | Military (-55C to 125C) |
| Programmability | OTP (windowless) | OTP (windowless) | UV-erasable (windowed) | UV-erasable (windowed) | OTP (windowless) | OTP (windowless) |
| Bidirectional I/O Pins | 64 | 64 | 64 | 64 | 64 | 64 |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
| Pin Count | 84 | 84 | 84 | 84 | 84 | 84 |
Key Differentiators
- Windowless OTP architecture suited for production volume (vs EPM5192ALC84-15)
- Industrial temperature grade for harsh environments (vs EPM5192ALC84-15)
- Faster -15 grade with full industrial qualification (vs EPM5192ALI84-20)
Design Notes
The EPM5192ALI84-15 is windowless OTP - once programmed it CANNOT be erased or reprogrammed. Always validate the JEDEC fuse map with a windowed EPM5192ALC84-15 (UV-erasable) prototype before committing to OTP volume production. Programming failures on OTP parts are permanent and the device is destroyed. Estimated prototype-to-production workflow: program LC84, UV-erase, iterate; once design is frozen, program LI84 for production.
The 84-pin PQCC (PLCC) J-Lead package uses standard 84-pin PLCC sockets (1.27 mm pitch). Recommended sockets include 3M 8400-series, Yamaichi IC149-084-Β£ series, and Wells-CTI 84-pin PLCC sockets. For field-replaceable designs, use a socketed footprint rather than direct PCB soldering to enable EOL replacement. Direct soldering of PLCC J-leads to PCB is feasible but complicates rework. The PLCC package is NOT pin-compatible with QFP/BGA modern CPLDs - any migration to MAX II/MAX V requires a complete PCB redesign.
The EPM5192ALI84-15 in industrial temperature grade operates from -40C to +85C ambient, with CMOS EPROM technology typical quiescent current of approximately 100-200 mA at 5V VCC depending on output switching activity. Estimated: at full 64 I/O switching at 5 MHz, dynamic current adds 30-50 mA. Provide at least 4 PCB VCC/GND decoupling capacitors (0.1 uF ceramic) placed within 5 mm of each package VCC pin to suppress switching noise on the EPROM programming lines and output banks. The PLCC package has moderate theta_JA (~40-50 C/W in still air); ensure adequate airflow in enclosed chassis.
Compliance Information
Compliance information not available in provided web data. The EPM5192ALI84-15 is a legacy Altera (now Intel) CMOS EPROM device from the 1990s; RoHS compliance for the LI84 suffix (industrial, OTP) was not confirmed in retrieved sources. Pre-2005 Altera products are commonly non-RoHS unless explicitly marked Pb-Free.
