EPM5192ALM84-20 vs EPM5192ALC84-20 Comparison
Detailed side-by-side comparison of EPM5192ALM84-20 by Altera and EPM5192ALC84-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5192ALM84-20 | EPM5192ALC84-20 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | MAX 5000 | — |
| Device Type | UV-Erasable/OTP Complex PLD (CPLD) | UV-Erasable/OTP Complex PLD (EPLD) |
| Macrocells | 192 | 192 |
| User I/O Pins | 64 | — |
| Dedicated Inputs | 7 | — |
| Total Inputs | 71 (64 I/O + 7 dedicated) | — |
| Maximum Clock Frequency | 66.7 MHz | — |
| Propagation Delay (tPD) | 33 ns | — |
| Process Technology | CMOS | CMOS |
| Package | 84-pin PQCC (PLCC), J-Lead, surface-mount | 84-pin PLCC (Plastic Leaded Chip Carrier) |
| Programmable Security Bit | Yes | — |
| Logic Voltage Compatibility | 5 V TTL | — |
| Configuration Memory | EPROM (UV-erasable, windowless in this package) | EPROM (UV-erasable) |
| Operating Temperature | [DATA_NEEDED: commercial/industrial/military grade] | — |
| RoHS Status | unknown (legacy Altera part) | [DATA_NEEDED: RoHS status not in provided web data] |
| Series | — | Altera MAX 5000 |
| Speed Grade | — | -20 (20 ns pin-to-pin delay) |
| Terminal Pitch | — | 1.270 mm |
| Terminal Form | — | J-bend |
| Package Code | — | QCCJ (PLCC-84) |
| Package Shape | — | Square |
| Temperature Grade | — | Commercial |
| Programming Method | — | UV-erase + EPROM (One-Time-Programmable option) |
| Logic Family | — | MAX 5000 EPLD |
| I/O Compatibility | — | TTL-compatible |
| Mounting Type | — | Surface Mount (PLCC socket-compatible) |