EPM5192AQM100-20 vs EPM5192AQC100-20 Comparison
Detailed side-by-side comparison of EPM5192AQM100-20 by Intel and EPM5192AQC100-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM5192AQM100-20 - MAX 5000 CPLD 64 I/O 33ns PQFP-100 | Intel / Altera
EPM5192AQM100-20 ObsoleteSpecification Comparison
| Parameter | EPM5192AQM100-20 | EPM5192AQC100-20 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $8.20 | $11.85 |
| Device Family | MAX 5000 (EPLD / classic CPLD) | MAX 5000 |
| Logic Elements | 192 macrocells across 12 Logic Array Blocks (LABs) | β |
| Number of LABs | 12 | β |
| User I/O Lines | 64 | β |
| Dedicated Inputs | 7 | β |
| Pin-to-Pin Propagation Delay (tPD) | 33 ns | β |
| Maximum Clock Frequency (fMAX) | 66.7 MHz | β |
| Package | 100-pin PQFP (JESD-30 code R-PQFP-G100) | 100-lead PQFP (R-PQFP-G100) |
| Mounting Type | Surface Mount | Surface Mount (PQFP) |
| Process Technology | CMOS EPROM-based | CMOS |
| Configuration Memory | On-chip EPROM (non-volatile, one-time programmable in this package) | β |
| Boundary-Scan Test | JTAG / IEEE 1149.1 compatible | β |
| External Clock Input | Yes (global clock pin) | β |
| Operating Temperature Grade | [DATA_NEEDED: explicit temperature grade from datasheet] | β |
| Supply Voltage | [DATA_NEEDED: VCC range from datasheet] | 5 V (typical, MAX 5000 family) |
| RoHS Status | [DATA_NEEDED: verified from manufacturer product page] | [DATA_NEEDED: RoHS status] |
| Product Type | β | Complex Programmable Logic Device (CPLD) |
| Macrocells | β | 192 |
| Maximum Operating Frequency | β | 66.7 MHz |
| Propagation Delay (tpd) | β | 33 ns |
| Terminal Pitch | β | 0.65 mm |
| Programming Technology | β | UV-Erasable / One-Time-Programmable (OTP) |
| Operating Temperature Range | β | [DATA_NEEDED: operating temperature range] |
| I/O Count | β | [DATA_NEEDED: usable I/O count] |
| Logic Array Blocks | β | Multiple LABs (per MAX 5000 architecture) |
| Lead-Free | β | [DATA_NEEDED: lead-free status] |
| MSL Level | β | [DATA_NEEDED: MSL rating] |