EPM5192AQM100-20 vs EPM5192AQC100-20 Vergleich
Detaillierter Direktvergleich von EPM5192AQM100-20 von Intel und EPM5192AQC100-20 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EPM5192AQM100-20 - MAX 5000 CPLD 64 I/O 33ns PQFP-100 | Intel / Altera
EPM5192AQM100-20 ObsoleteSpezifikationsvergleich
| Parameter | EPM5192AQM100-20 | EPM5192AQC100-20 |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $8,20 | $11,85 |
| Device Family | MAX 5000 (EPLD / classic CPLD) | MAX 5000 |
| Logic Elements | 192 macrocells across 12 Logic Array Blocks (LABs) | — |
| Number of LABs | 12 | — |
| User I/O Lines | 64 | — |
| Dedicated Inputs | 7 | — |
| Pin-to-Pin Propagation Delay (tPD) | 33 ns | — |
| Maximum Clock Frequency (fMAX) | 66.7 MHz | — |
| Gehäuse | 100-pin PQFP (JESD-30 code R-PQFP-G100) | 100-lead PQFP (R-PQFP-G100) |
| Montageart | Surface Mount | Surface Mount (PQFP) |
| Process Technology | CMOS EPROM-based | CMOS |
| Configuration Memory | On-chip EPROM (non-volatile, one-time programmable in this package) | — |
| Boundary-Scan Test | JTAG / IEEE 1149.1 compatible | — |
| External Clock Input | Yes (global clock pin) | — |
| Operating Temperature Grade | [DATA_NEEDED: explicit temperature grade from datasheet] | — |
| Versorgungsspannung | [DATA_NEEDED: VCC range from datasheet] | 5 V (typical, MAX 5000 family) |
| RoHS-Status | [DATA_NEEDED: verified from manufacturer product page] | [DATA_NEEDED: RoHS status] |
| Product Type | — | Complex Programmable Logic Device (CPLD) |
| Macrocells | — | 192 |
| Maximum Operating Frequency | — | 66.7 MHz |
| Propagation Delay (tpd) | — | 33 ns |
| Terminal Pitch | — | 0.65 mm |
| Programming Technology | — | UV-Erasable / One-Time-Programmable (OTP) |
| Betriebstemperaturbereich | — | [DATA_NEEDED: operating temperature range] |
| I/O Count | — | [DATA_NEEDED: usable I/O count] |
| Logic Array Blocks | — | Multiple LABs (per MAX 5000 architecture) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| MSL-Level | — | [DATA_NEEDED: MSL rating] |